mirror of https://github.com/YosysHQ/yosys.git
426 lines
16 KiB
Plaintext
426 lines
16 KiB
Plaintext
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-- Executing script file `fifo.ys' --
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$ yosys fifo.v
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-- Parsing `fifo.v' using frontend ` -vlog2k' --
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1. Executing Verilog-2005 frontend: fifo.v
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Parsing Verilog input from `fifo.v' to AST representation.
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Storing AST representation for module `$abstract\addr_gen'.
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Storing AST representation for module `$abstract\fifo'.
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Successfully finished Verilog frontend.
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echo on
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yosys> hierarchy -top addr_gen
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2. Executing HIERARCHY pass (managing design hierarchy).
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3. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'.
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Generating RTLIL representation for module `\addr_gen'.
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3.1. Analyzing design hierarchy..
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Top module: \addr_gen
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3.2. Analyzing design hierarchy..
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Top module: \addr_gen
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Removing unused module `$abstract\fifo'.
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Removing unused module `$abstract\addr_gen'.
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Removed 2 unused modules.
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yosys> select -module addr_gen
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yosys [addr_gen]> select -list
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addr_gen
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addr_gen/$1\addr[7:0]
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addr_gen/$add$fifo.v:19$3_Y
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addr_gen/$eq$fifo.v:16$2_Y
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addr_gen/$0\addr[7:0]
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addr_gen/addr
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addr_gen/rst
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addr_gen/clk
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addr_gen/en
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addr_gen/$add$fifo.v:19$3
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addr_gen/$eq$fifo.v:16$2
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addr_gen/$proc$fifo.v:0$4
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addr_gen/$proc$fifo.v:12$1
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yosys [addr_gen]> select t:*
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yosys [addr_gen]*> select -list
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addr_gen/$add$fifo.v:19$3
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addr_gen/$eq$fifo.v:16$2
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yosys [addr_gen]*> select -set new_cells %
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yosys [addr_gen]*> select -clear
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yosys> show -format dot -prefix addr_gen_show addr_gen
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4. Generating Graphviz representation of design.
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Writing dot description to `addr_gen_show.dot'.
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Dumping module addr_gen to page 1.
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yosys> show -format dot -prefix new_cells_show -notitle @new_cells
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5. Generating Graphviz representation of design.
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Writing dot description to `new_cells_show.dot'.
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Dumping selected parts of module addr_gen to page 1.
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yosys> show -color maroon3 @new_cells -color cornflowerblue p:* -notitle -format dot -prefix addr_gen_hier
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6. Generating Graphviz representation of design.
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Writing dot description to `addr_gen_hier.dot'.
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Dumping module addr_gen to page 1.
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yosys> proc -noopt
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7. Executing PROC pass (convert processes to netlists).
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yosys> proc_clean
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7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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yosys> proc_rmdead
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7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 2 switch rules as full_case in process $proc$fifo.v:12$1 in module addr_gen.
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Removed a total of 0 dead cases.
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yosys> proc_prune
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7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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Removed 0 redundant assignments.
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Promoted 1 assignment to connection.
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yosys> proc_init
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7.4. Executing PROC_INIT pass (extract init attributes).
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Found init rule in `\addr_gen.$proc$fifo.v:0$4'.
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Set init value: \addr = 8'00000000
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yosys> proc_arst
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7.5. Executing PROC_ARST pass (detect async resets in processes).
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Found async reset \rst in `\addr_gen.$proc$fifo.v:12$1'.
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yosys> proc_rom
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7.6. Executing PROC_ROM pass (convert switches to ROMs).
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Converted 0 switches.
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<suppressed ~2 debug messages>
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yosys> proc_mux
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7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `\addr_gen.$proc$fifo.v:0$4'.
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Creating decoders for process `\addr_gen.$proc$fifo.v:12$1'.
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1/1: $0\addr[7:0]
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yosys> proc_dlatch
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7.8. Executing PROC_DLATCH pass (convert process syncs to latches).
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yosys> proc_dff
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7.9. Executing PROC_DFF pass (convert process syncs to FFs).
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Creating register for signal `\addr_gen.\addr' using process `\addr_gen.$proc$fifo.v:12$1'.
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created $adff cell `$procdff$10' with positive edge clock and positive level reset.
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yosys> proc_memwr
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7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
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yosys> proc_clean
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7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Removing empty process `addr_gen.$proc$fifo.v:0$4'.
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Found and cleaned up 2 empty switches in `\addr_gen.$proc$fifo.v:12$1'.
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Removing empty process `addr_gen.$proc$fifo.v:12$1'.
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Cleaned up 2 empty switches.
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yosys> select -set new_cells t:$mux t:*dff
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yosys> show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_proc
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8. Generating Graphviz representation of design.
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Writing dot description to `addr_gen_proc.dot'.
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Dumping module addr_gen to page 1.
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yosys> opt_expr
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9. Executing OPT_EXPR pass (perform const folding).
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Optimizing module addr_gen.
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yosys> clean
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Removed 0 unused cells and 4 unused wires.
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yosys> select -set new_cells t:$eq
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yosys> show -color cornflowerblue @new_cells -notitle -format dot -prefix addr_gen_clean
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10. Generating Graphviz representation of design.
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Writing dot description to `addr_gen_clean.dot'.
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Dumping module addr_gen to page 1.
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yosys> design -reset
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yosys> read_verilog fifo.v
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11. Executing Verilog-2005 frontend: fifo.v
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Parsing Verilog input from `fifo.v' to AST representation.
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Generating RTLIL representation for module `\addr_gen'.
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Generating RTLIL representation for module `\fifo'.
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Successfully finished Verilog frontend.
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yosys> hierarchy -check -top fifo
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12. Executing HIERARCHY pass (managing design hierarchy).
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12.1. Analyzing design hierarchy..
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Top module: \fifo
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Used module: \addr_gen
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Parameter \MAX_DATA = 256
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12.2. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'.
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Parameter \MAX_DATA = 256
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Generating RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'.
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Parameter \MAX_DATA = 256
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Found cached RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'.
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12.3. Analyzing design hierarchy..
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Top module: \fifo
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Used module: $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000
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12.4. Analyzing design hierarchy..
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Top module: \fifo
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Used module: $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000
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Removing unused module `\addr_gen'.
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Removed 1 unused modules.
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yosys> proc
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13. Executing PROC pass (convert processes to netlists).
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yosys> proc_clean
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13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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yosys> proc_rmdead
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13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 2 switch rules as full_case in process $proc$fifo.v:62$24 in module fifo.
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Marked 1 switch rules as full_case in process $proc$fifo.v:36$16 in module fifo.
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Marked 2 switch rules as full_case in process $proc$fifo.v:12$32 in module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
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Removed a total of 0 dead cases.
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yosys> proc_prune
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13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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Removed 0 redundant assignments.
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Promoted 6 assignments to connections.
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yosys> proc_init
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13.4. Executing PROC_INIT pass (extract init attributes).
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Found init rule in `\fifo.$proc$fifo.v:0$31'.
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Set init value: \count = 9'000000000
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Found init rule in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'.
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Set init value: \addr = 8'00000000
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yosys> proc_arst
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13.5. Executing PROC_ARST pass (detect async resets in processes).
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Found async reset \rst in `\fifo.$proc$fifo.v:62$24'.
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Found async reset \rst in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'.
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yosys> proc_rom
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13.6. Executing PROC_ROM pass (convert switches to ROMs).
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Converted 0 switches.
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<suppressed ~5 debug messages>
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yosys> proc_mux
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13.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `\fifo.$proc$fifo.v:0$31'.
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Creating decoders for process `\fifo.$proc$fifo.v:62$24'.
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1/1: $0\count[8:0]
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Creating decoders for process `\fifo.$proc$fifo.v:36$16'.
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1/3: $1$memwr$\data$fifo.v:38$15_EN[7:0]$22
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2/3: $1$memwr$\data$fifo.v:38$15_DATA[7:0]$21
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3/3: $1$memwr$\data$fifo.v:38$15_ADDR[7:0]$20
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Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'.
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Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'.
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1/1: $0\addr[7:0]
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yosys> proc_dlatch
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13.8. Executing PROC_DLATCH pass (convert process syncs to latches).
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yosys> proc_dff
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13.9. Executing PROC_DFF pass (convert process syncs to FFs).
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Creating register for signal `\fifo.\count' using process `\fifo.$proc$fifo.v:62$24'.
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created $adff cell `$procdff$55' with positive edge clock and positive level reset.
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Creating register for signal `\fifo.\rdata' using process `\fifo.$proc$fifo.v:36$16'.
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created $dff cell `$procdff$56' with positive edge clock.
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Creating register for signal `\fifo.$memwr$\data$fifo.v:38$15_ADDR' using process `\fifo.$proc$fifo.v:36$16'.
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created $dff cell `$procdff$57' with positive edge clock.
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Creating register for signal `\fifo.$memwr$\data$fifo.v:38$15_DATA' using process `\fifo.$proc$fifo.v:36$16'.
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created $dff cell `$procdff$58' with positive edge clock.
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Creating register for signal `\fifo.$memwr$\data$fifo.v:38$15_EN' using process `\fifo.$proc$fifo.v:36$16'.
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created $dff cell `$procdff$59' with positive edge clock.
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Creating register for signal `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.\addr' using process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'.
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created $adff cell `$procdff$60' with positive edge clock and positive level reset.
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yosys> proc_memwr
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13.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
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yosys> proc_clean
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13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Removing empty process `fifo.$proc$fifo.v:0$31'.
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Found and cleaned up 2 empty switches in `\fifo.$proc$fifo.v:62$24'.
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Removing empty process `fifo.$proc$fifo.v:62$24'.
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Found and cleaned up 1 empty switch in `\fifo.$proc$fifo.v:36$16'.
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Removing empty process `fifo.$proc$fifo.v:36$16'.
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Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'.
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Found and cleaned up 2 empty switches in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'.
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Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'.
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Cleaned up 5 empty switches.
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yosys> opt_expr -keepdc
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13.12. Executing OPT_EXPR pass (perform const folding).
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Optimizing module fifo.
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Optimizing module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
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yosys> select -set new_cells t:$memrd
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yosys> show -color maroon3 c:fifo_reader -color cornflowerblue @new_cells -notitle -format dot -prefix rdata_proc o:rdata %ci*
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14. Generating Graphviz representation of design.
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Writing dot description to `rdata_proc.dot'.
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Dumping selected parts of module fifo to page 1.
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yosys> flatten
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15. Executing FLATTEN pass (flatten design).
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Deleting now unused module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
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<suppressed ~2 debug messages>
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yosys> clean
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Removed 3 unused cells and 25 unused wires.
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yosys> select -set rdata_path o:rdata %ci*
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yosys> select -set new_cells @rdata_path o:rdata %ci3 %d i:* %d
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yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_flat @rdata_path
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16. Generating Graphviz representation of design.
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Writing dot description to `rdata_flat.dot'.
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Dumping selected parts of module fifo to page 1.
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yosys> opt_dff
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17. Executing OPT_DFF pass (perform DFF optimizations).
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Adding EN signal on $procdff$55 ($adff) from module fifo (D = $0\count[8:0], Q = \count).
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Adding EN signal on $flatten\fifo_writer.$procdff$60 ($adff) from module fifo (D = $flatten\fifo_writer.$procmux$51_Y, Q = \fifo_writer.addr).
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Adding EN signal on $flatten\fifo_reader.$procdff$60 ($adff) from module fifo (D = $flatten\fifo_reader.$procmux$51_Y, Q = \fifo_reader.addr).
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yosys> select -set new_cells t:$adffe
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yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_adffe o:rdata %ci*
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18. Generating Graphviz representation of design.
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Writing dot description to `rdata_adffe.dot'.
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Dumping selected parts of module fifo to page 1.
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yosys> wreduce
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19. Executing WREDUCE pass (reducing word size of cells).
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Removed top 31 bits (of 32) from port B of cell fifo.$add$fifo.v:66$27 ($add).
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Removed top 23 bits (of 32) from port Y of cell fifo.$add$fifo.v:66$27 ($add).
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Removed top 31 bits (of 32) from port B of cell fifo.$sub$fifo.v:68$30 ($sub).
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Removed top 23 bits (of 32) from port Y of cell fifo.$sub$fifo.v:68$30 ($sub).
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Removed top 1 bits (of 2) from port B of cell fifo.$auto$opt_dff.cc:195:make_patterns_logic$66 ($ne).
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Removed cell fifo.$flatten\fifo_writer.$procmux$53 ($mux).
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Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$34 ($add).
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Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$34 ($add).
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Removed cell fifo.$flatten\fifo_reader.$procmux$53 ($mux).
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Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$34 ($add).
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Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$34 ($add).
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Removed top 23 bits (of 32) from wire fifo.$add$fifo.v:66$27_Y.
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Removed top 24 bits (of 32) from wire fifo.$flatten\fifo_reader.$add$fifo.v:19$34_Y.
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yosys> show -notitle -format dot -prefix rdata_wreduce o:rdata %ci*
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20. Generating Graphviz representation of design.
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Writing dot description to `rdata_wreduce.dot'.
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Dumping selected parts of module fifo to page 1.
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yosys> opt_clean
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21. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \fifo..
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Removed 0 unused cells and 4 unused wires.
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<suppressed ~1 debug messages>
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yosys> memory_dff
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22. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
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Checking read port `\data'[0] in module `\fifo': merging output FF to cell.
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Write port 0: non-transparent.
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yosys> select -set new_cells t:$memrd_v2
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yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdata %ci*
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23. Generating Graphviz representation of design.
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Writing dot description to `rdata_memrdv2.dot'.
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Dumping selected parts of module fifo to page 1.
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yosys> alumacc
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24. Executing ALUMACC pass (create $alu and $macc cells).
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Extracting $alu and $macc cells in module fifo:
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creating $macc model for $add$fifo.v:66$27 ($add).
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creating $macc model for $flatten\fifo_reader.$add$fifo.v:19$34 ($add).
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creating $macc model for $flatten\fifo_writer.$add$fifo.v:19$34 ($add).
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creating $macc model for $sub$fifo.v:68$30 ($sub).
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creating $alu model for $macc $sub$fifo.v:68$30.
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creating $alu model for $macc $flatten\fifo_writer.$add$fifo.v:19$34.
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creating $alu model for $macc $flatten\fifo_reader.$add$fifo.v:19$34.
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creating $alu model for $macc $add$fifo.v:66$27.
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creating $alu cell for $add$fifo.v:66$27: $auto$alumacc.cc:485:replace_alu$80
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creating $alu cell for $flatten\fifo_reader.$add$fifo.v:19$34: $auto$alumacc.cc:485:replace_alu$83
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creating $alu cell for $flatten\fifo_writer.$add$fifo.v:19$34: $auto$alumacc.cc:485:replace_alu$86
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creating $alu cell for $sub$fifo.v:68$30: $auto$alumacc.cc:485:replace_alu$89
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created 4 $alu and 0 $macc cells.
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yosys> select -set new_cells t:$alu t:$macc
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yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci*
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25. Generating Graphviz representation of design.
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Writing dot description to `rdata_alumacc.dot'.
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Dumping selected parts of module fifo to page 1.
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yosys> memory_collect
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26. Executing MEMORY_COLLECT pass (generating $mem cells).
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yosys> select -set new_cells t:$mem_v2
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yosys> select -set rdata_path @new_cells %ci*:-$mem_v2[WR_DATA,WR_ADDR,WR_EN] @new_cells %co* %%
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yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse @rdata_path
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27. Generating Graphviz representation of design.
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Writing dot description to `rdata_coarse.dot'.
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Dumping selected parts of module fifo to page 1.
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