mirror of https://github.com/YosysHQ/yosys.git
33 lines
464 B
Verilog
33 lines
464 B
Verilog
module test_1(
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input [7:0] a, b, c,
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input s, x,
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output [7:0] y1, y2
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);
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wire [7:0] t1, t2;
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assign t1 = s ? a*b : 0, t2 = !s ? b*c : 0;
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assign y1 = x ? t2 : t1, y2 = x ? t1 : t2;
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endmodule
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module test_2(
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input s,
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input [7:0] a, b, c,
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output reg [7:0] y
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);
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always @* begin
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y <= 'bx;
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if (s) begin
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if (a * b > 8)
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y <= b / c;
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else
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y <= c / b;
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end else begin
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if (b * c > 8)
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y <= a / b;
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else
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y <= b / a;
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end
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end
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endmodule
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