yosys/frontends/verilog
rherveille ce7db661a8
Added cast to type support (#4284)
2024-09-29 17:03:01 -04:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Treat all bison warnings as errors in verilog front-end 2020-07-15 11:57:31 +02:00
const2ast.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
preproc.cc set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
preproc.h verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
verilog_frontend.cc read_verilog: Add missing defaults for flags 2024-05-07 20:25:36 +02:00
verilog_frontend.h verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_lexer.l fmt: %t/$time support 2023-08-11 04:46:52 +02:00
verilog_parser.y Added cast to type support (#4284) 2024-09-29 17:03:01 -04:00