yosys/frontends/verilog
Marcelina Kościelnicka 52cbf1bea5 verilog: Support tri/triand/trior wire types.
These are, by the standard, just aliases for wire/wand/wor.

Fixes #2918.
2021-08-06 21:35:43 +02:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Treat all bison warnings as errors in verilog front-end 2020-07-15 11:57:31 +02:00
const2ast.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
preproc.cc verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
preproc.h verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
verilog_frontend.cc verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_frontend.h verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_lexer.l verilog: Support tri/triand/trior wire types. 2021-08-06 21:35:43 +02:00
verilog_parser.y Add support for parsing the SystemVerilog 'bind' construct 2021-07-16 09:31:39 -04:00