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Jim Lawson 171c425cf9 Fix FIRRTL to Verilog process instance subfield assignment. 
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
 		2019-02-25 16:18:13 -08:00
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.gitignore
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README Another block of spelling fixes 2015-08-14 23:27:05 +02:00
code_hdl_models_GrayCounter.v
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code_hdl_models_arbiter.v Fixed CRLF line endings 2015-08-13 09:35:00 +02:00
code_hdl_models_arbiter_tb.v Some fixes in tests/asicworld/*_tb.v 2016-05-20 17:13:11 +02:00
code_hdl_models_cam.v
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code_hdl_models_clk_div.v
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code_hdl_models_clk_div_45.v
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code_hdl_models_d_ff_gates.v
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code_hdl_models_d_latch_gates.v
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code_hdl_models_decoder_2to4_gates.v
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code_hdl_models_decoder_using_assign.v
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code_hdl_models_decoder_using_case.v
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code_hdl_models_dff_async_reset.v
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code_hdl_models_dff_sync_reset.v
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code_hdl_models_encoder_4to2_gates.v
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code_hdl_models_encoder_using_case.v
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code_hdl_models_encoder_using_if.v
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code_hdl_models_full_adder_gates.v
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code_hdl_models_full_subtracter_gates.v
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code_hdl_models_gray_counter.v
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code_hdl_models_half_adder_gates.v
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code_hdl_models_lfsr.v
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code_hdl_models_lfsr_updown.v
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code_hdl_models_mux_2to1_gates.v
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code_hdl_models_mux_using_assign.v
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code_hdl_models_mux_using_case.v
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code_hdl_models_mux_using_if.v
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code_hdl_models_one_hot_cnt.v
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code_hdl_models_parallel_crc.v
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code_hdl_models_parity_using_assign.v
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code_hdl_models_parity_using_bitwise.v
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code_hdl_models_parity_using_function.v
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code_hdl_models_pri_encoder_using_assign.v
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code_hdl_models_rom_using_case.v
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code_hdl_models_serial_crc.v
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code_hdl_models_tff_async_reset.v
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code_hdl_models_tff_sync_reset.v
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code_hdl_models_uart.v
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code_hdl_models_up_counter.v
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code_hdl_models_up_counter_load.v
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code_hdl_models_up_down_counter.v
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code_specman_switch_fabric.v
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code_tidbits_asyn_reset.v
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code_tidbits_blocking.v
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code_tidbits_fsm_using_always.v
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code_tidbits_fsm_using_function.v
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code_tidbits_fsm_using_single_always.v
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code_tidbits_nonblocking.v
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code_tidbits_reg_combo_example.v
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code_tidbits_reg_seq_example.v
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code_tidbits_syn_reset.v
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code_tidbits_wire_example.v
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code_verilog_tutorial_addbit.v
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code_verilog_tutorial_always_example.v
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code_verilog_tutorial_bus_con.v
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code_verilog_tutorial_comment.v
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code_verilog_tutorial_counter.v Fixed CRLF line endings 2015-08-13 09:35:00 +02:00
code_verilog_tutorial_counter_tb.v Some fixes in tests/asicworld/*_tb.v 2016-05-20 17:13:11 +02:00
code_verilog_tutorial_d_ff.v
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code_verilog_tutorial_decoder.v
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code_verilog_tutorial_decoder_always.v
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code_verilog_tutorial_escape_id.v
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code_verilog_tutorial_explicit.v
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code_verilog_tutorial_first_counter.v
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code_verilog_tutorial_first_counter_tb.v Some fixes in tests/asicworld/*_tb.v 2016-05-20 17:13:11 +02:00
code_verilog_tutorial_flip_flop.v
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code_verilog_tutorial_fsm_full.v
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code_verilog_tutorial_fsm_full_tb.v Some fixes in tests/asicworld/*_tb.v 2016-05-20 17:13:11 +02:00
code_verilog_tutorial_good_code.v
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code_verilog_tutorial_if_else.v
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code_verilog_tutorial_multiply.v
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code_verilog_tutorial_mux_21.v
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code_verilog_tutorial_n_out_primitive.v
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code_verilog_tutorial_parallel_if.v
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code_verilog_tutorial_parity.v
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code_verilog_tutorial_simple_function.v
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code_verilog_tutorial_simple_if.v
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code_verilog_tutorial_task_global.v
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code_verilog_tutorial_tri_buf.v
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code_verilog_tutorial_v2k_reg.v
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code_verilog_tutorial_which_clock.v
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run-test.sh Append (instead of over-writing) EXTRA_FLAGS 2019-02-15 11:56:51 -08:00
xfirrtl Fix FIRRTL to Verilog process instance subfield assignment. 2019-02-25 16:18:13 -08:00

README 

Borrowed Verilog examples from http://www.asic-world.com/.