mirror of https://github.com/YosysHQ/yosys.git
65 lines
1.3 KiB
Verilog
65 lines
1.3 KiB
Verilog
module example (
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input clk,
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input SW1,
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input SW2,
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output LED1,
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output LED2,
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output LED3,
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output LED4,
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output AA, AB, AC, AD,
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output AE, AF, AG, CA
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);
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localparam BITS = 8;
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localparam LOG2DELAY = 22;
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reg [BITS+LOG2DELAY-1:0] counter = 0;
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reg [BITS-1:0] outcnt;
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always @(posedge clk) begin
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counter <= counter + SW1 + SW2 + 1;
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outcnt <= counter >> LOG2DELAY;
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end
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assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);
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// assign CA = counter[10];
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// seg7enc seg7encinst (
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// .seg({AA, AB, AC, AD, AE, AF, AG}),
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// .dat(CA ? outcnt[3:0] : outcnt[7:4])
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// );
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assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[6:4]);
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assign CA = outcnt[7];
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endmodule
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module seg7enc (
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input [3:0] dat,
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output [6:0] seg
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);
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reg [6:0] seg_inv;
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always @* begin
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seg_inv = 0;
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case (dat)
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4'h0: seg_inv = 7'b 0111111;
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4'h1: seg_inv = 7'b 0000110;
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4'h2: seg_inv = 7'b 1011011;
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4'h3: seg_inv = 7'b 1001111;
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4'h4: seg_inv = 7'b 1100110;
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4'h5: seg_inv = 7'b 1101101;
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4'h6: seg_inv = 7'b 1111101;
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4'h7: seg_inv = 7'b 0000111;
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4'h8: seg_inv = 7'b 1111111;
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4'h9: seg_inv = 7'b 1101111;
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4'hA: seg_inv = 7'b 1110111;
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4'hB: seg_inv = 7'b 1111100;
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4'hC: seg_inv = 7'b 0111001;
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4'hD: seg_inv = 7'b 1011110;
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4'hE: seg_inv = 7'b 1111001;
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4'hF: seg_inv = 7'b 1110001;
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endcase
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end
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assign seg = ~seg_inv;
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endmodule
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