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yosys/techlibs/microchip
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C77874 d0cd01adfe fixed typos, build with makefile succeeds 2024-07-04 09:33:58 -07:00
..
tests changes made to filenames + references 2024-07-04 08:53:41 -07:00
LSRAM.txt changes made to filenames + references 2024-07-04 08:53:41 -07:00
LSRAM_map.v changes made to filenames + references 2024-07-04 08:53:41 -07:00
Makefile.inc fixed typos, build with makefile succeeds 2024-07-04 09:33:58 -07:00
arith_map.v changes made to filenames + references 2024-07-04 08:53:41 -07:00
brams_defs.vh changes made to filenames + references 2024-07-04 08:53:41 -07:00
cells_map.v changes made to filenames + references 2024-07-04 08:53:41 -07:00
cells_sim.v Merge branch 'mchp' of https://github.com/tony-min-1/yosys into change_filenames 2024-07-04 09:00:38 -07:00
microchip_dffopt.cc changes made to filenames + references 2024-07-04 08:53:41 -07:00
polarfire_dsp_map.v changes made to filenames + references 2024-07-04 08:53:41 -07:00
synth_microchip.cc changes made to filenames + references 2024-07-04 08:53:41 -07:00
uSRAM.txt changes made to filenames + references 2024-07-04 08:53:41 -07:00
uSRAM_map.v changes made to filenames + references 2024-07-04 08:53:41 -07:00