Claire Xenia Wolf d0b5dfa6ef Add bufnorm pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>		2024-09-17 10:46:20 +02:00
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cmds	Merge pull request #4538 from RCoeurjoly/verific_bounds	2024-09-12 13:04:04 +02:00
equiv	equiv_simple: Take FFs into account for driver map	2024-02-21 12:05:52 +01:00
fsm	add option to fsm_detect to ignore self-resetting	2023-01-30 16:12:53 +01:00
hierarchy	cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter	2024-07-29 10:26:02 +02:00
memory	memory_map: Explain `-iattr` better	2024-03-06 15:15:37 +01:00
opt	Merge pull request #4176 from povik/opt_expr-performance	2024-07-15 16:10:25 +02:00
pmgen	Merge pull request #4452 from phsauter/shiftadd-underflow-fix	2024-08-19 15:45:46 +02:00
proc	proc_dff: respect sync rule priorities when generating complex dffsrs	2024-08-28 15:48:07 +01:00
sat	add -fst-noinit flag to sim for not initializing the state from the fst file	2024-08-21 11:03:29 +01:00
techmap	Add bufnorm pass	2024-09-17 10:46:20 +02:00
tests	cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter	2024-07-29 10:26:02 +02:00