Miodrag Milanović 3e14e67374 Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase ... VHDL is case insensitive, make sure netlist name is proper		2024-07-29 16:44:13 +02:00
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aiger	read_aiger: Fix incorrect read of binary Aiger without outputs	2024-04-29 14:06:58 +01:00
ast	ast: don't suggest use in external projects	2024-07-18 16:37:14 +02:00
blif	Issue a warning instead of a syntax error for blif delay constraints	2024-01-23 16:25:16 +00:00
json	fix handling of escaped chars in json backend and frontend	2022-02-18 17:13:09 +01:00
liberty	liberty: Support for IO liberty files for verification	2024-06-19 21:12:42 +02:00
rpc	Fitting help messages to 80 character width	2022-08-24 10:40:57 +12:00
rtlil	Specify minimum bison version 3.0+	2021-10-01 21:18:33 -06:00
verific	Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase	2024-07-29 16:44:13 +02:00
verilog	read_verilog: Add missing defaults for flags	2024-05-07 20:25:36 +02:00