mirror of https://github.com/YosysHQ/yosys.git
112 lines
4.0 KiB
C++
112 lines
4.0 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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#include "kernel/consteval.h"
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#include "kernel/log.h"
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#include <sstream>
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#include <stdlib.h>
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#include <stdio.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &next_priority)
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{
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for (auto sr : proc->syncs)
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{
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for (auto memwr : sr->mem_write_actions) {
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RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr));
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cell->attributes = memwr.attributes;
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cell->setParam(ID::MEMID, Const(memwr.memid.str()));
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cell->setParam(ID::ABITS, GetSize(memwr.address));
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cell->setParam(ID::WIDTH, GetSize(memwr.data));
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cell->setParam(ID::PRIORITY, next_priority[memwr.memid]++);
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cell->setPort(ID::ADDR, memwr.address);
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cell->setPort(ID::DATA, memwr.data);
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SigSpec enable = memwr.enable;
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for (auto sr2 : proc->syncs) {
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if (sr2->type == RTLIL::SyncType::ST0) {
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log_assert(sr2->mem_write_actions.empty());
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enable = mod->Mux(NEW_ID, Const(State::S0, GetSize(enable)), enable, sr2->signal);
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} else if (sr2->type == RTLIL::SyncType::ST1) {
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log_assert(sr2->mem_write_actions.empty());
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enable = mod->Mux(NEW_ID, enable, Const(State::S0, GetSize(enable)), sr2->signal);
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}
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}
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cell->setPort(ID::EN, enable);
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if (sr->type == RTLIL::SyncType::STa) {
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cell->setPort(ID::CLK, State::Sx);
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cell->setParam(ID::CLK_ENABLE, State::S0);
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cell->setParam(ID::CLK_POLARITY, State::Sx);
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} else if (sr->type == RTLIL::SyncType::STp) {
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cell->setPort(ID::CLK, sr->signal);
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cell->setParam(ID::CLK_ENABLE, State::S1);
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cell->setParam(ID::CLK_POLARITY, State::S1);
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} else if (sr->type == RTLIL::SyncType::STn) {
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cell->setPort(ID::CLK, sr->signal);
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cell->setParam(ID::CLK_ENABLE, State::S1);
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cell->setParam(ID::CLK_POLARITY, State::S0);
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} else {
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log_error("process memory write with unsupported sync type in %s.%s", log_id(mod), log_id(proc));
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}
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}
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sr->mem_write_actions.clear();
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}
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}
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struct ProcMemWrPass : public Pass {
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ProcMemWrPass() : Pass("proc_memwr", "extract memory writes from processes") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" proc_memwr [selection]\n");
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log("\n");
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log("This pass converts memory writes in processes into $memwr cells.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing PROC_MEMWR pass (convert process memory writes to cells).\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules()) {
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dict<IdString, int> next_priority;
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for (auto cell : module->cells()) {
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if (cell->type == ID($memwr)) {
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IdString memid = cell->parameters.at(ID::MEMID).decode_string();
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int priority = cell->parameters.at(ID::PRIORITY).as_int();
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if (priority >= next_priority[memid])
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next_priority[memid] = priority + 1;
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}
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}
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for (auto &proc_it : module->processes)
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if (design->selected(module, proc_it.second))
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proc_memwr(module, proc_it.second, next_priority);
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}
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}
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} ProcMemWrPass;
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PRIVATE_NAMESPACE_END
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