mirror of https://github.com/YosysHQ/yosys.git
36 lines
515 B
Verilog
36 lines
515 B
Verilog
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module counter1(clk, rst, ping);
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input clk, rst;
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output ping;
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reg [31:0] count;
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always @(posedge clk) begin
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if (rst)
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count <= 0;
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else
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count <= count + 1;
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end
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assign ping = &count;
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endmodule
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module counter2(clk, rst, ping);
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input clk, rst;
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output ping;
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reg [31:0] count;
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integer i;
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reg carry;
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always @(posedge clk) begin
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carry = 1;
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for (i = 0; i < 32; i = i+1) begin
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count[i] <= !rst & (count[i] ^ carry);
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carry = count[i] & carry;
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end
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end
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assign ping = &count;
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endmodule
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