mirror of https://github.com/YosysHQ/yosys.git
72 lines
1.9 KiB
Verilog
72 lines
1.9 KiB
Verilog
`default_nettype none
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(* techmap_celltype = "$alu" *)
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module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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function integer round_up4;
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input integer N;
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begin
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round_up4 = ((N + 3) / 4) * 4;
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end
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endfunction
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localparam Y_WIDTH4 = round_up4(Y_WIDTH);
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(* force_downto *)
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wire [Y_WIDTH4-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH4-1:0] BB = BI ? ~B_buf : B_buf;
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(* force_downto *)
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wire [Y_WIDTH4-1:0] BX = B_buf;
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(* force_downto *)
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wire [Y_WIDTH4:0] C = {CO, CI};
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(* force_downto *)
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wire [Y_WIDTH4-1:0] FCO, Y1;
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genvar i;
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generate for (i = 0; i < Y_WIDTH4; i = i + 4) begin:slice
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NX_CY cy_i (
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.CI(C[i]),
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.A1(AA[i]), .A2(AA[i+1]), .A3(AA[i+2]), .A4(AA[i+3]),
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.B1(BB[i]), .B2(BB[i+1]), .B3(BB[i+2]), .B4(BB[i+3]),
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.S1(Y1[i]), .S2(Y1[i+1]), .S3(Y1[i+2]), .S4(Y1[i+3]),
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.CO(FCO[i])
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);
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assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
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if (i+1 < Y_WIDTH)
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assign CO[i+1] = (AA[i+1] && BB[i+1]) || (C[i+1] && (AA[i+1] || BB[i+1]));
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if (i+2 < Y_WIDTH)
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assign CO[i+2] = (AA[i+2] && BB[i+2]) || (C[i+2] && (AA[i+2] || BB[i+2]));
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if (i+3 < Y_WIDTH)
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assign CO[i+3] = FCO[i];
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end endgenerate
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assign X = AA ^ BB;
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assign Y = Y1[Y_WIDTH-1:0];
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endmodule
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