mirror of https://github.com/YosysHQ/yosys.git
58 lines
1.5 KiB
Plaintext
58 lines
1.5 KiB
Plaintext
read_verilog -icells <<EOT
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module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
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parameter DEPTH = 1;
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parameter [DEPTH-1:0] INIT = 0;
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parameter CLKPOL = 1;
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parameter ENPOL = 2;
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wire pos_clk = C == CLKPOL;
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reg pos_en;
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always @(E)
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if (ENPOL == 2) pos_en = 1'b1;
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else pos_en = (E == ENPOL[0]);
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reg [DEPTH-1:0] r;
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always @(posedge pos_clk)
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if (pos_en)
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r <= {r[DEPTH-2:0], D};
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assign Q = r[L];
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assign SO = r[DEPTH-1];
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endmodule
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EOT
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read_verilog +/xilinx/cells_sim.v
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proc
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design -save model
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test_pmgen -generate xilinx_srl.fixed
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hierarchy -top pmtest_xilinx_srl_pm_fixed
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flatten; opt_clean
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design -save gold
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xilinx_srl -fixed
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techmap -autoproc -map %model
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design -stash gate
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design -copy-from gold -as gold pmtest_xilinx_srl_pm_fixed
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design -copy-from gate -as gate pmtest_xilinx_srl_pm_fixed
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dff2dffe -unmap # sat does not support flops-with-enable yet
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miter -equiv -flatten -make_assert gold gate miter
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sat -set-init-zero -seq 5 -verify -prove-asserts miter
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design -load model
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test_pmgen -generate xilinx_srl.variable
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hierarchy -top pmtest_xilinx_srl_pm_variable
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flatten; opt_clean
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design -save gold
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xilinx_srl -variable
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techmap -autoproc -map %model
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design -stash gate
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design -copy-from gold -as gold pmtest_xilinx_srl_pm_variable
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design -copy-from gate -as gate pmtest_xilinx_srl_pm_variable
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dff2dffe -unmap # sat does not support flops-with-enable yet
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miter -equiv -flatten -make_assert gold gate miter
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sat -set-init-zero -seq 5 -verify -prove-asserts miter
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