mirror of https://github.com/YosysHQ/yosys.git
24 lines
862 B
Plaintext
24 lines
862 B
Plaintext
read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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design -save orig
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 8 t:LUT2
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select -assert-count 2 t:CARRY4
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select -assert-none t:LUT2 t:CARRY4 %% t:* %D
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design -load orig
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3s -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 8 t:LUT2
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select -assert-count 6 t:MUXCY
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select -assert-count 8 t:XORCY
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select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D
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