mirror of https://github.com/YosysHQ/yosys.git
100 lines
4.6 KiB
ReStructuredText
100 lines
4.6 KiB
ReStructuredText
What is Yosys
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=============
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.. TODO: rewrite to not be a thesis abstract
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:Abstract:
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Most of today's digital design is done in HDL code (mostly Verilog or
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VHDL) and with the help of HDL synthesis tools.
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In special cases such as synthesis for coarse-grain cell libraries or
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when testing new synthesis algorithms it might be necessary to write a
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custom HDL synthesis tool or add new features to an existing one. In
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these cases the availability of a Free and Open Source (FOSS) synthesis
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tool that can be used as basis for custom tools would be helpful.
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In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys)
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was developed. This document covers the design and implementation of
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this tool. At the moment the main focus of Yosys lies on the high-level
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aspects of digital synthesis. The pre-existing FOSS logic-synthesis tool
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ABC is used by Yosys to perform advanced gate-level optimizations.
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An evaluation of Yosys based on real-world designs is included. It is
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shown that Yosys can be used as-is to synthesize such designs. The
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results produced by Yosys in this tests where successfully verified
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using formal verification and are comparable in quality to the results
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produced by a commercial synthesis tool.
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This document was originally published as bachelor thesis at the Vienna
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University of Technology :cite:p:`BACC`.
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Yosys is a tool for synthesising (behavioural) Verilog HDL code to target
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architecture netlists. Yosys aims at a wide range of application domains and
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thus must be flexible and easy to adapt to new tasks.
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What you can do with Yosys
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--------------------------
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The extended Yosys universe
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---------------------------
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In no particular order:
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- SBY for formal verification
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- EQY for equivalence checking
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- MCY for mutation coverage
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History of Yosys
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----------------
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.. TODO: copypaste
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A Hardware Description Language (HDL) is a computer language used to describe
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circuits. A HDL synthesis tool is a computer program that takes a formal
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description of a circuit written in an HDL as input and generates a netlist that
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implements the given circuit as output.
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Currently the most widely used and supported HDLs for digital circuits are
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Verilog :cite:p:`Verilog2005,VerilogSynth` and :abbr:`VHDL (VHSIC HDL, where
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VHSIC is an acronym for Very-High-Speed Integrated Circuits)`
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:cite:p:`VHDL,VHDLSynth`. Both HDLs are used for test and verification purposes
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as well as logic synthesis, resulting in a set of synthesizable and a set of
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non-synthesizable language features. In this document we only look at the
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synthesizable subset of the language features.
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In recent work on heterogeneous coarse-grain reconfigurable logic
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:cite:p:`intersynth` the need for a custom application-specific HDL synthesis
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tool emerged. It was soon realised that a synthesis tool that understood Verilog
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or VHDL would be preferred over a synthesis tool for a custom HDL. Given an
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existing Verilog or VHDL front end, the work for writing the necessary
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additional features and integrating them in an existing tool can be estimated to
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be about the same as writing a new tool with support for a minimalistic custom
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HDL.
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The proposed custom HDL synthesis tool should be licensed under a Free and Open
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Source Software (FOSS) licence. So an existing FOSS Verilog or VHDL synthesis
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tool would have been needed as basis to build upon. The main advantages of
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choosing Verilog or VHDL is the ability to synthesize existing HDL code and to
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mitigate the requirement for circuit-designers to learn a new language. In order
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to take full advantage of any existing FOSS Verilog or VHDL tool, such a tool
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would have to provide a feature-complete implementation of the synthesizable HDL
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subset.
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Basic RTL synthesis is a well understood field :cite:p:`LogicSynthesis`. Lexing,
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parsing and processing of computer languages :cite:p:`Dragonbook` is a
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thoroughly researched field. All the information required to write such tools
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has been openly available for a long time, and it is therefore likely that a
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FOSS HDL synthesis tool with a feature-complete Verilog or VHDL front end must
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exist which can be used as a basis for a custom RTL synthesis tool.
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Due to the author's preference for Verilog over VHDL it was decided early on to
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go for Verilog instead of VHDL [#]_. So the existing FOSS Verilog synthesis
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tools were evaluated. The results of this evaluation are utterly devastating.
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Therefore a completely new Verilog synthesis tool was implemented and is
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recommended as basis for custom synthesis tools. This is the tool that is
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discussed in this document.
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.. [#]
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A quick investigation into FOSS VHDL tools yielded similar grim results for
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FOSS VHDL synthesis tools.
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