mirror of https://github.com/YosysHQ/yosys.git
227 lines
8.2 KiB
C++
227 lines
8.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/consteval.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <algorithm>
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namespace {
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/* this should only be used for regression testing of ConstEval -- see tests/xsthammer */
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struct BruteForceEquivChecker
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{
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RTLIL::Module *mod1, *mod2;
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RTLIL::SigSpec mod1_inputs, mod1_outputs;
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RTLIL::SigSpec mod2_inputs, mod2_outputs;
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int counter, errors;
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bool ignore_x_mod1;
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void run_checker(RTLIL::SigSpec &inputs)
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{
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if (inputs.width < mod1_inputs.width) {
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RTLIL::SigSpec inputs0 = inputs, inputs1 = inputs;
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inputs0.append(RTLIL::Const(0, 1));
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inputs1.append(RTLIL::Const(1, 1));
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run_checker(inputs0);
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run_checker(inputs1);
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return;
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}
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inputs.optimize();
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ConstEval ce1(mod1), ce2(mod2);
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ce1.set(mod1_inputs, inputs.as_const());
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ce2.set(mod2_inputs, inputs.as_const());
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RTLIL::SigSpec sig1 = mod1_outputs, undef1;
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RTLIL::SigSpec sig2 = mod2_outputs, undef2;
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if (!ce1.eval(sig1, undef1))
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log("Failed ConstEval of module 1 outputs at signal %s (input: %s = %s).\n",
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log_signal(undef1), log_signal(mod1_inputs), log_signal(inputs));
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if (!ce2.eval(sig2, undef2))
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log("Failed ConstEval of module 2 outputs at signal %s (input: %s = %s).\n",
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log_signal(undef2), log_signal(mod1_inputs), log_signal(inputs));
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if (ignore_x_mod1) {
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sig1.expand(), sig2.expand();
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for (size_t i = 0; i < sig1.chunks.size(); i++)
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if (sig1.chunks.at(i) == RTLIL::SigChunk(RTLIL::State::Sx))
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sig2.chunks.at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
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sig1.optimize(), sig2.optimize();
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}
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if (sig1 != sig2) {
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log("Found counter-example (ignore_x_mod1 = %s):\n", ignore_x_mod1 ? "active" : "inactive");
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log(" Module 1: %s = %s => %s = %s\n", log_signal(mod1_inputs), log_signal(inputs), log_signal(mod1_outputs), log_signal(sig1));
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log(" Module 2: %s = %s => %s = %s\n", log_signal(mod2_inputs), log_signal(inputs), log_signal(mod2_outputs), log_signal(sig2));
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errors++;
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}
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counter++;
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}
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BruteForceEquivChecker(RTLIL::Module *mod1, RTLIL::Module *mod2, bool ignore_x_mod1) :
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mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1)
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{
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log("Checking for equivialence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
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for (auto &w : mod1->wires)
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{
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RTLIL::Wire *wire1 = w.second;
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if (wire1->port_id == 0)
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continue;
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if (mod2->wires.count(wire1->name) == 0)
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log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", wire1->name.c_str());
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RTLIL::Wire *wire2 = mod2->wires.at(wire1->name);
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if (wire1->width != wire2->width || wire1->port_input != wire2->port_input || wire1->port_output != wire2->port_output)
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log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", wire1->name.c_str());
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if (wire1->port_input) {
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mod1_inputs.append(wire1);
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mod2_inputs.append(wire2);
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} else {
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mod1_outputs.append(wire1);
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mod2_outputs.append(wire2);
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}
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}
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RTLIL::SigSpec inputs;
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run_checker(inputs);
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}
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};
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} /* namespace */
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struct EvalPass : public Pass {
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EvalPass() : Pass("eval", "evaluate the circuit given an input") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" eval [options] [selection]\n");
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log("\n");
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log("This command evaluates the value of a signal given the value of all required\n");
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log("inputs.\n");
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log("\n");
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log(" -set <signal> <value>\n");
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log(" set the specified signal to the specified value.\n");
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log("\n");
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log(" -show <signal>\n");
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log(" show the value for the specified signal. if no -show option is passed\n");
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log(" then all output ports of the current module are used.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::vector<std::pair<std::string, std::string>> sets;
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std::vector<std::string> shows;
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log_header("Executing EVAL pass (evaluate the circuit given an input).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-set" && argidx+2 < args.size()) {
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std::string lhs = args[++argidx].c_str();
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std::string rhs = args[++argidx].c_str();
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sets.push_back(std::pair<std::string, std::string>(lhs, rhs));
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continue;
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}
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if (args[argidx] == "-show" && argidx+1 < args.size()) {
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shows.push_back(args[++argidx]);
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continue;
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}
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if ((args[argidx] == "-brute_force_equiv_checker" || args[argidx] == "-brute_force_equiv_checker_x") && argidx+2 < args.size()) {
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/* this should only be used for regression testing of ConstEval -- see tests/xsthammer */
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std::string mod1_name = RTLIL::escape_id(args[++argidx]);
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std::string mod2_name = RTLIL::escape_id(args[++argidx]);
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extra_args(args, argidx, design);
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if (design->modules.count(mod1_name) == 0)
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log_error("Can't find module `%s'!\n", mod1_name.c_str());
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if (design->modules.count(mod2_name) == 0)
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log_error("Can't find module `%s'!\n", mod2_name.c_str());
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BruteForceEquivChecker checker(design->modules.at(mod1_name), design->modules.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
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if (checker.errors > 0)
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log_cmd_error("Modules are not equivialent!\n");
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log("Verified %s = %s (using brute-force check on %d cases).\n",
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mod1_name.c_str(), mod2_name.c_str(), checker.counter);
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return;
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}
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break;
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}
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extra_args(args, argidx, design);
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RTLIL::Module *module = NULL;
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for (auto &mod_it : design->modules)
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if (design->selected(mod_it.second)) {
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if (module)
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log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
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RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first));
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module = mod_it.second;
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}
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if (module == NULL)
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log_cmd_error("Can't perform EVAL on an empty selection!\n");
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ConstEval ce(module);
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RTLIL::SigSpec show_signal, show_value, undef_signal;
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for (auto &it : sets) {
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RTLIL::SigSpec lhs, rhs;
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if (!RTLIL::SigSpec::parse(lhs, module, it.first))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.first.c_str());
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if (!RTLIL::SigSpec::parse(rhs, module, it.second))
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log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str());
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if (!rhs.is_fully_const())
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log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second.c_str());
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if (lhs.width != rhs.width)
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log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
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it.first.c_str(), log_signal(lhs), lhs.width, it.second.c_str(), log_signal(rhs), rhs.width);
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ce.set(lhs, rhs.as_const());
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}
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for (auto &it : shows) {
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RTLIL::SigSpec sig;
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if (!RTLIL::SigSpec::parse(sig, module, it))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.c_str());
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show_signal.append(sig);
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}
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if (shows.size() == 0) {
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for (auto &it : module->wires)
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if (it.second->port_output)
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show_signal.append(it.second);
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}
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show_signal.optimize();
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show_value = show_signal;
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if (!ce.eval(show_value, undef_signal))
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log("Failed to evaluate signal %s: Missing value for %s.\n", log_signal(show_signal), log_signal(undef_signal));
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else
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log("Eval result: %s = %s.\n", log_signal(show_signal), log_signal(show_value));
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}
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} EvalPass;
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