mirror of https://github.com/YosysHQ/yosys.git
62 lines
1.3 KiB
Verilog
62 lines
1.3 KiB
Verilog
module top(
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input wire [3:0] inp,
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output wire [3:0] out1, out2, out3, out4, out5,
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output reg [3:0] out6
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);
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function automatic [3:0] flip;
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input [3:0] inp;
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flip = ~inp;
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endfunction
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function automatic [3:0] help;
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input [3:0] inp;
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help = flip(inp);
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endfunction
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// while loops are const-eval-only
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function automatic [3:0] loop;
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input [3:0] inp;
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reg [3:0] val;
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begin
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val = inp;
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loop = 1;
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while (val != inp) begin
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loop = loop * 2;
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val = val + 1;
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end
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end
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endfunction
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// not const-eval-only, despite calling a const-eval-only function
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function automatic [3:0] help_mul;
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input [3:0] inp;
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help_mul = inp * loop(2);
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endfunction
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// can be elaborated so long as exp is a constant
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function automatic [3:0] pow_flip_a;
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input [3:0] base, exp;
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begin
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pow_flip_a = 1;
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if (exp > 0)
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pow_flip_a = base * pow_flip_a(flip(base), exp - 1);
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end
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endfunction
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function automatic [3:0] pow_flip_b;
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input [3:0] base, exp;
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begin
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out6[exp] = base & 1;
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pow_flip_b = 1;
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if (exp > 0)
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pow_flip_b = base * pow_flip_b(flip(base), exp - 1);
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end
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endfunction
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assign out1 = flip(flip(inp));
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assign out2 = help(flip(inp));
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assign out3 = help_mul(inp);
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assign out4 = pow_flip_a(flip(inp), 3);
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assign out5 = pow_flip_b(2, 2);
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endmodule
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