mirror of https://github.com/YosysHQ/yosys.git
226 lines
7.0 KiB
C++
226 lines
7.0 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static bool is_formal_celltype(const std::string &celltype)
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{
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if(celltype == "assert" || celltype == "assume" || celltype == "live" || celltype == "fair" || celltype == "cover")
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return true;
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else
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return false;
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}
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static void add_formal(RTLIL::Module *module, const std::string &celltype, const std::string &name, const std::string &enable_name)
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{
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std::string escaped_name = RTLIL::escape_id(name);
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std::string escaped_enable_name = (enable_name != "") ? RTLIL::escape_id(enable_name) : "";
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RTLIL::Wire *wire = module->wire(escaped_name);
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log_assert(is_formal_celltype(celltype));
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if (wire == nullptr) {
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log_error("Could not find wire with name \"%s\".\n", name.c_str());
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}
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else {
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RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
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formal_cell->setPort(ID(A), wire);
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if(enable_name == "") {
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formal_cell->setPort(ID(EN), State::S1);
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log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str());
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}
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else {
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RTLIL::Wire *enable_wire = module->wire(escaped_enable_name);
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if(enable_wire == nullptr)
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log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str());
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formal_cell->setPort(ID(EN), enable_wire);
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log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str());
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}
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}
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}
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static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
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{
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RTLIL::Wire *wire = nullptr;
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name = RTLIL::escape_id(name);
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if (module->count_id(name) != 0)
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{
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wire = module->wire(name);
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if (wire != nullptr && wire->width != width)
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wire = nullptr;
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if (wire != nullptr && wire->port_input != flag_input)
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wire = nullptr;
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if (wire != nullptr && wire->port_output != flag_output)
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wire = nullptr;
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if (wire == nullptr)
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log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());
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log("Module %s already has such an object.\n", module->name.c_str());
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}
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else
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{
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wire = module->addWire(name, width);
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wire->port_input = flag_input;
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wire->port_output = flag_output;
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if (flag_input || flag_output) {
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module->fixup_ports();
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}
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log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
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}
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if (!flag_global)
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return;
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for (auto cell : module->cells())
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{
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RTLIL::Module *mod = design->module(cell->type);
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if (mod == nullptr)
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continue;
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if (!design->selected_whole_module(mod->name))
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continue;
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if (mod->get_blackbox_attribute())
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continue;
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if (cell->hasPort(name))
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continue;
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cell->setPort(name, wire);
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log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), cell->name.c_str(), cell->type.c_str());
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}
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}
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struct AddPass : public Pass {
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AddPass() : Pass("add", "add objects to the design") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" add <command> [selection]\n");
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log("\n");
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log("This command adds objects to the design. It operates on all fully selected\n");
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log("modules. So e.g. 'add -wire foo' will add a wire foo to all selected modules.\n");
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log("\n");
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log("\n");
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log(" add {-wire|-input|-inout|-output} <name> <width> [selection]\n");
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log("\n");
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log("Add a wire (input, inout, output port) with the given name and width. The\n");
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log("command will fail if the object exists already and has different properties\n");
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log("than the object to be created.\n");
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log("\n");
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log("\n");
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log(" add -global_input <name> <width> [selection]\n");
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log("\n");
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log("Like 'add -input', but also connect the signal between instances of the\n");
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log("selected modules.\n");
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log("\n");
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log("\n");
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log(" add {-assert|-assume|-live|-fair|-cover} <name1> [-if <name2>]\n");
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log("\n");
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log("Add an $assert, $assume, etc. cell connected to a wire named name1, with its\n");
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log("enable signal optionally connected to a wire named name2 (default: 1'b1).\n");
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log("\n");
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log("\n");
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log(" add -mod <name[s]>\n");
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log("\n");
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log("Add module[s] with the specified name[s].\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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std::string command;
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std::string arg_name;
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std::string enable_name = "";
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bool arg_flag_input = false;
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bool arg_flag_output = false;
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bool arg_flag_global = false;
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bool mod_mode = false;
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int arg_width = 0;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-wire" || arg == "-input" || arg == "-inout" || arg == "-output" || arg == "-global_input") {
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if (argidx+2 >= args.size())
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break;
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command = "wire";
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if (arg == "-input" || arg == "-inout" || arg == "-global_input")
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arg_flag_input = true;
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if (arg == "-output" || arg == "-inout")
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arg_flag_output = true;
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if (arg == "-global_input")
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arg_flag_global = true;
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arg_name = args[++argidx];
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arg_width = atoi(args[++argidx].c_str());
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continue;
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}
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if (arg == "-mod") {
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mod_mode = true;
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argidx++;
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break;
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}
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if (arg.length() > 0 && arg[0] == '-' && is_formal_celltype(arg.substr(1))) {
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if (argidx + 1 >= args.size())
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break;
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command = arg.substr(1);
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arg_name = args[++argidx];
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if (argidx + 2 < args.size() && args[argidx + 1] == "-if") {
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enable_name = args[argidx + 2];
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argidx += 2;
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}
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continue;
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}
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break;
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}
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if (mod_mode) {
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for (; argidx < args.size(); argidx++)
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design->addModule(RTLIL::escape_id(args[argidx]));
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return;
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}
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extra_args(args, argidx, design);
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for (auto module : design->modules())
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{
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log_assert(module != nullptr);
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if (!design->selected_whole_module(module->name))
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continue;
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if (module->get_bool_attribute("\\blackbox"))
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continue;
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if (is_formal_celltype(command))
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add_formal(module, command, arg_name, enable_name);
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else if (command == "wire")
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add_wire(design, module, arg_name, arg_width, arg_flag_input, arg_flag_output, arg_flag_global);
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}
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}
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} AddPass;
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PRIVATE_NAMESPACE_END
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