yosys/frontends/verilog
N. Engelhardt e069259a53
Merge pull request #1679 from thasti/delay-parsing
Fix crash on wire declaration with delay
2020-02-13 12:01:27 +01:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Read bigger Verilog files. 2019-05-18 14:20:30 +03:00
const2ast.cc Fix handling of z_digit "?" and fix optimization of cmp with "z" 2019-09-13 13:39:39 +02:00
preproc.cc Fixed some missing "verilog_" in documentation 2019-12-13 10:17:05 -03:00
verilog_frontend.cc Add "verilog_defines -list" and "verilog_defines -reset" 2019-10-21 13:35:56 +02:00
verilog_frontend.h Add specify parser 2019-04-23 21:36:59 +02:00
verilog_lexer.l sv: Improve handling of wildcard port connections 2020-02-02 16:12:33 +00:00
verilog_parser.y Merge pull request #1679 from thasti/delay-parsing 2020-02-13 12:01:27 +01:00