This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
cb45f8b69d
yosys
/
tests
/
verilog
/
ifdef_unterminated.ys
5 lines
97 B
Plaintext
Raw
Blame
History
logger -expect error "Unterminated preprocessor conditional!" 1
read_verilog <<EOF
`ifndef a
EOF
Reference in New Issue
View Git Blame
Copy Permalink