mirror of https://github.com/YosysHQ/yosys.git
92 lines
4.1 KiB
Verilog
92 lines
4.1 KiB
Verilog
`default_nettype none
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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(* force_downto *)
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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localparam [15:0] INIT = {{2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}},
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{2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}};
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NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
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.I1(A[0]), .I2(1'b0), .I3(1'b0), .I4(1'b0));
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end else
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if (WIDTH == 2) begin
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localparam [15:0] INIT = {{4{LUT[3:0]}}, {4{LUT[3:0]}}, {4{LUT[3:0]}}, {4{LUT[3:0]}}};
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NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
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.I1(A[0]), .I2(A[1]), .I3(1'b0), .I4(1'b0), );
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end else
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if (WIDTH == 3) begin
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localparam [15:0] INIT = {{8{LUT[7:0]}}, {8{LUT[7:0]}}};
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NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
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.I1(A[0]), .I2(A[1]), .I3(A[2]), .I4(1'b0));
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end else
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if (WIDTH == 4) begin
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NX_LUT #(.lut_table(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I1(A[0]), .I2(A[1]), .I3(A[2]), .I4(A[3]));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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(* techmap_celltype = "$_DFF_[NP]P[01]_" *)
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module \$_DFF_xxxx_ (input D, C, R, output Q);
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parameter _TECHMAP_CELLTYPE_ = "";
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localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == "N";
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localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == "1";
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q));
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endmodule
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(* techmap_celltype = "$_SDFF_[NP]P[01]_" *)
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module \$_SDFF_xxxx_ (input D, C, R, output Q);
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parameter _TECHMAP_CELLTYPE_ = "";
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localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == "N";
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localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == "1";
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q));
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endmodule
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(* techmap_celltype = "$_DFFE_[NP]P[01]P_" *)
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module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
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parameter _TECHMAP_CELLTYPE_ = "";
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localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == "N";
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localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == "1";
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q));
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endmodule
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(* techmap_celltype = "$_SDFFE_[NP]P[01]P_" *)
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module \$_SDFFE_xxxx_ (input D, C, R, E, output Q);
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parameter _TECHMAP_CELLTYPE_ = "";
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localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == "N";
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localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == "1";
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q));
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endmodule
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module \$_DFF_P_ (input D, C, output Q);
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
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endmodule
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module \$_DFF_N_ (input D, C, output Q);
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
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endmodule
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module \$_DFFE_PP_ (input D, C, E, output Q);
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
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endmodule
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module \$_DFFE_NP_ (input D, C, E, output Q);
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
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endmodule
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