mirror of https://github.com/YosysHQ/yosys.git
393 lines
8.3 KiB
Verilog
393 lines
8.3 KiB
Verilog
//(* blackbox *)
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//module NX_LUT(I1, I2, I3, I4, O);
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// input I1;
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// input I2;
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// input I3;
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// input I4;
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// output O;
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// parameter lut_table = 16'b0000000000000000;
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//endmodule
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//(* blackbox *)
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//module NX_CY(A1, A2, A3, A4, B1, B2, B3, B4, CI, CO, S1, S2, S3, S4);
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// input A1;
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// input A2;
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// input A3;
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// input A4;
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// input B1;
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// input B2;
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// input B3;
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// input B4;
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// input CI;
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// output CO;
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// output S1;
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// output S2;
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// output S3;
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// output S4;
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// parameter add_carry = 0;
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//endmodule
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// Bypass mode of NX_GCK_U
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(* blackbox *)
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module NX_BD(I, O);
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input I;
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output O;
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parameter mode = "global_lowskew";
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endmodule
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//(* blackbox *)
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//module NX_DFF(I, CK, L, R, O);
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// input CK;
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// input I;
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// input L;
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// output O;
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// input R;
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// parameter dff_ctxt = 1'b0;
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// parameter dff_edge = 1'b0;
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// parameter dff_init = 1'b0;
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// parameter dff_load = 1'b0;
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// parameter dff_sync = 1'b0;
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// parameter dff_type = 1'b0;
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//endmodule
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// Special mode of NX_DFF
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(* blackbox *)
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module NX_BFF(I, O);
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input I;
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output O;
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endmodule
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(* blackbox *)
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module NX_DFR(I, CK, L, R, O);
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input CK;
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input I;
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input L;
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output O;
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input R;
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parameter data_inv = 1'b0;
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parameter dff_edge = 1'b0;
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parameter dff_init = 1'b0;
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parameter dff_load = 1'b0;
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parameter dff_sync = 1'b0;
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parameter dff_type = 1'b0;
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parameter iobname = "";
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parameter location = "";
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parameter mode = 0;
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parameter path = 0;
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parameter ring = 0;
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endmodule
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// Special mode of NX_DFR
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(* blackbox *)
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module NX_BFR(I, O);
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input I;
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output O;
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parameter data_inv = 1'b0;
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parameter iobname = "";
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parameter location = "";
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parameter mode = 0;
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parameter path = 0;
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parameter ring = 0;
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endmodule
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(* blackbox *)
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module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
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, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
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, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3
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, AO4, AO5, AO6, AO7, AO8, AO9, AO10, AO11, AO12, AO13, AO14, AO15, AO16, AO17, AO18, AO19, AO20, AO21, AO22, AO23, AO24
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, BO1, BO2, BO3, BO4, BO5, BO6, BO7, BO8, BO9, BO10, BO11, BO12, BO13, BO14, BO15, BO16, BO17, BO18, BO19, BO20, BO21
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, BO22, BO23, BO24, AA1, AA2, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, ACS, AWE
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, AR, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8, BA9, BA10, BA11, BA12, BA13, BA14, BA15, BA16, BCS, BWE, BR);
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input AA1;
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input AA10;
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input AA11;
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input AA12;
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input AA13;
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input AA14;
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input AA15;
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input AA16;
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input AA2;
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input AA3;
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input AA4;
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input AA5;
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input AA6;
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input AA7;
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input AA8;
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input AA9;
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input ACK;
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input ACKC;
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input ACKD;
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input ACKR;
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output ACOR;
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input ACS;
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output AERR;
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input AI1;
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input AI10;
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input AI11;
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input AI12;
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input AI13;
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input AI14;
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input AI15;
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input AI16;
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input AI17;
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input AI18;
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input AI19;
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input AI2;
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input AI20;
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input AI21;
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input AI22;
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input AI23;
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input AI24;
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input AI3;
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input AI4;
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input AI5;
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input AI6;
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input AI7;
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input AI8;
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input AI9;
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output AO1;
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output AO10;
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output AO11;
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output AO12;
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output AO13;
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output AO14;
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output AO15;
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output AO16;
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output AO17;
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output AO18;
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output AO19;
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output AO2;
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output AO20;
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output AO21;
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output AO22;
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output AO23;
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output AO24;
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output AO3;
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output AO4;
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output AO5;
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output AO6;
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output AO7;
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output AO8;
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output AO9;
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input AR;
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input AWE;
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input BA1;
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input BA10;
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input BA11;
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input BA12;
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input BA13;
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input BA14;
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input BA15;
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input BA16;
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input BA2;
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input BA3;
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input BA4;
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input BA5;
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input BA6;
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input BA7;
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input BA8;
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input BA9;
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input BCK;
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input BCKC;
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input BCKD;
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input BCKR;
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output BCOR;
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input BCS;
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output BERR;
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input BI1;
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input BI10;
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input BI11;
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input BI12;
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input BI13;
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input BI14;
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input BI15;
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input BI16;
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input BI17;
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input BI18;
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input BI19;
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input BI2;
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input BI20;
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input BI21;
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input BI22;
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input BI23;
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input BI24;
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input BI3;
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input BI4;
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input BI5;
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input BI6;
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input BI7;
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input BI8;
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input BI9;
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output BO1;
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output BO10;
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output BO11;
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output BO12;
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output BO13;
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output BO14;
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output BO15;
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output BO16;
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output BO17;
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output BO18;
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output BO19;
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output BO2;
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output BO20;
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output BO21;
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output BO22;
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output BO23;
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output BO24;
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output BO3;
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output BO4;
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output BO5;
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output BO6;
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output BO7;
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output BO8;
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output BO9;
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input BR;
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input BWE;
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parameter mcka_edge = 1'b0;
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parameter mckb_edge = 1'b0;
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parameter mem_ctxt = "";
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parameter pcka_edge = 1'b0;
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parameter pckb_edge = 1'b0;
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parameter pipe_ia = 1'b0;
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parameter pipe_ib = 1'b0;
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parameter pipe_oa = 1'b0;
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parameter pipe_ob = 1'b0;
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parameter raw_config0 = 4'b0000;
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parameter raw_config1 = 16'b0000000000000000;
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parameter raw_l_enable = 1'b0;
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parameter raw_l_extend = 4'b0000;
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parameter raw_u_enable = 1'b0;
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parameter raw_u_extend = 8'b00000000;
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parameter std_mode = "";
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endmodule
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// NX_RAM related
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(* blackbox *)
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module NX_ECC(CKD, CHK, COR, ERR);
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input CHK;
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input CKD;
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output COR;
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output ERR;
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endmodule
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//TODO
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(* blackbox *)
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module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA);
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input [1:0] DS;
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input GS;
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output [2:0] GVDN;
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output [2:0] GVIN;
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output [2:0] GVON;
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input [5:0] LA;
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output [3:0] PA;
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endmodule
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//TODO
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(* blackbox *)
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module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID);
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input DCK;
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output [5:0] DID;
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input [5:0] DRA;
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input [5:0] DRI;
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input DRL;
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output [5:0] DRO;
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input [1:0] DS;
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input FCK;
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input [4:0] I;
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output IO;
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input R;
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input SCK;
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parameter data_size = 5;
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parameter differential = "";
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parameter drive = "";
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parameter location = "";
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parameter locked = 1'b0;
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parameter outputCapacity = "";
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parameter outputDelayLine = "";
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parameter slewRate = "";
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parameter spath_dynamic = 1'b0;
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parameter standard = "";
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endmodule
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//TODO
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(* blackbox *)
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module NX_DES(FCK, SCK, R, IO, DCK, DRL, DIG, FZ, FLD, FLG, O, DS, DRA, DRI, DRO, DID);
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input DCK;
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output [5:0] DID;
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input DIG;
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input [5:0] DRA;
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input [5:0] DRI;
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input DRL;
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output [5:0] DRO;
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input [1:0] DS;
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input FCK;
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output FLD;
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output FLG;
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input FZ;
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input IO;
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output [4:0] O;
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input R;
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input SCK;
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parameter data_size = 5;
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parameter differential = "";
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parameter dpath_dynamic = 1'b0;
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parameter drive = "";
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parameter inputDelayLine = "";
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parameter inputSignalSlope = "";
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parameter location = "";
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parameter locked = 1'b0;
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parameter standard = "";
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parameter termination = "";
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parameter terminationReference = "";
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parameter turbo = "";
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parameter weakTermination = "";
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endmodule
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//TODO
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(* blackbox *)
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module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD, FLG, I, O, DS, DRA, DRI, DRO
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, DID);
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input CCK;
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input CI;
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input CL;
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input CR;
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input DCK;
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output [5:0] DID;
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input DIG;
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input [5:0] DRA;
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input [5:0] DRI;
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input DRL;
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output [5:0] DRO;
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input [1:0] DS;
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input FCK;
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output FLD;
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output FLG;
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input FZ;
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input [4:0] I;
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inout IO;
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output [4:0] O;
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input RRX;
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input RTX;
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input SCK;
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parameter cpath_registered = 1'b0;
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parameter data_size = 5;
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parameter differential = "";
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parameter dpath_dynamic = 1'b0;
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parameter drive = "";
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parameter inputDelayLine = "";
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parameter inputSignalSlope = "";
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parameter location = "";
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parameter locked = 1'b0;
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parameter outputCapacity = "";
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parameter outputDelayLine = "";
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parameter slewRate = "";
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parameter spath_dynamic = 1'b0;
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parameter standard = "";
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parameter termination = "";
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parameter terminationReference = "";
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parameter turbo = "";
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parameter weakTermination = "";
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endmodule
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