mirror of https://github.com/YosysHQ/yosys.git
44 lines
957 B
Verilog
44 lines
957 B
Verilog
module $__NX_RAM_ (...);
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parameter INIT = 0;
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parameter OPTION_RESETMODE = "SYNC";
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parameter PORT_A_WIDTH = 9;
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parameter PORT_A_CLK_POL = 1;
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parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input PORT_A_WR_EN;
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input PORT_A_RD_SRST;
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input PORT_A_RD_ARST;
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input [12:0] PORT_A_ADDR;
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input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
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output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
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parameter PORT_B_WIDTH = 9;
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parameter PORT_B_CLK_POL = 1;
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parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input PORT_B_WR_EN;
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input PORT_B_RD_SRST;
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input PORT_B_RD_ARST;
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input [12:0] PORT_B_ADDR;
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input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
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output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
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NX_RAM_WRAP #(
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) _TECHMAP_REPLACE_ (
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.ACK(PORT_A_CLK),
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.AA(PORT_A_ADDR),
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.AI(PORT_A_WR_DATA),
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.AO(PORT_A_RD_DATA),
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.BCK(PORT_B_CLK),
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.BA(PORT_B_ADDR),
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.BI(PORT_B_WR_DATA),
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.BO(PORT_B_RD_DATA)
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);
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endmodule |