Clifford Wolf cb1d439d10 Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master		2017-09-26 13:48:13 +02:00
..
.gitignore	Updated .gitignore file for ilang and verilog frontends	2014-10-15 01:14:38 +02:00
Makefile.inc	Adjust makefiles to work with out-of-tree builds	2015-08-12 15:04:44 +02:00
const2ast.cc	Fixed segfault on invalid verilog constant 1'b_	2015-09-22 08:13:09 +02:00
preproc.cc	Adding support for string macros and macros with arguments after include	2017-09-21 18:25:02 +01:00
verilog_frontend.cc	Add a paragraph about pre-defined macros to read_verilog help message	2017-07-21 14:34:53 +02:00
verilog_frontend.h	Remember global declarations and defines accross read_verilog calls	2016-11-15 12:42:43 +01:00
verilog_lexer.l	Fix ignoring of simulation timings so that invalid module parameters cause syntax errors	2017-09-26 01:52:59 +02:00
verilog_parser.y	Fix ignoring of simulation timings so that invalid module parameters cause syntax errors	2017-09-26 01:52:59 +02:00