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yosys
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ca53fba44a
yosys
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passes
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Clifford Wolf
ca53fba44a
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
..
cmds
More intuitive handling of "cd .." for singleton modules
2017-08-19 00:15:12 +02:00
equiv
Fix equiv_simple, old behavior now available with "equiv_simple -short"
2017-04-28 18:57:53 +02:00
fsm
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
hierarchy
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
memory
Typo fix.
2016-09-08 10:57:16 +03:00
opt
Mostly coding style related fixes in rmports pass
2017-08-15 11:32:35 +02:00
proc
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
sat
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
techmap
abc: Allow +/ filenames in the abc command
2017-08-14 12:11:11 -07:00
tests
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00