mirror of https://github.com/YosysHQ/yosys.git
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Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days. |
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| README | ||
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| example.v | ||
README
This is a simple example for Yosys synthesis targeting the ZED FPGA development board [1, 2]. Simple script for xst-based synthesis (incl. generation of reference edif files) and uploading to the board can be found here [3]. [1] http://www.zedboard.org/ [2] https://www.xilinx.com/zynq/ [3] http://verilog.james.walms.co.uk/