mirror of https://github.com/YosysHQ/yosys.git
327 lines
15 KiB
C++
327 lines
15 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 Alberto Gonzalez <boqwxp@airmail.cc>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct GliftPass : public Pass {
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private:
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bool opt_create, opt_sketchify, opt_taintconstants, opt_keepoutputs, opt_nomodeloptimize;
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std::vector<std::string> args;
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std::vector<std::string>::size_type argidx;
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std::vector<RTLIL::Wire *> new_taint_outputs;
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std::vector<RTLIL::SigSpec> meta_mux_selects;
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RTLIL::Module *module;
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void parse_args() {
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-create") {
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opt_create = true;
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continue;
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}
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if (args[argidx] == "-sketchify") {
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opt_sketchify = true;
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continue;
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}
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if (args[argidx] == "-taint-constants") {
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opt_taintconstants = true;
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continue;
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}
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if (args[argidx] == "-keep-outputs") {
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opt_keepoutputs = true;
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continue;
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}
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if (args[argidx] == "-no-model-optimize") {
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opt_nomodeloptimize = true;
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continue;
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}
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break;
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}
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if(!opt_create && !opt_sketchify) log_cmd_error("One of `-create` or `-sketchify` must be specified.\n");
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if(opt_create && opt_sketchify) log_cmd_error("Only one of `-create` or `-sketchify` may be specified.\n");
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}
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RTLIL::SigSpec get_corresponding_taint_signal(RTLIL::SigSpec sig) {
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RTLIL::SigSpec ret;
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//Get the connected wire for the cell port:
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log_assert(sig.is_wire() || sig.is_fully_const());
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log_assert(sig.is_wire() || sig.is_fully_const());
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//Get a SigSpec for the corresponding taint signal for the cell port, creating one if necessary:
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if (sig.is_wire()) {
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RTLIL::Wire *w = module->wire(sig.as_wire()->name.str() + "_t");
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if (w == nullptr) w = module->addWire(sig.as_wire()->name.str() + "_t", 1);
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ret = w;
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}
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else if (sig.is_fully_const() && opt_taintconstants)
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ret = RTLIL::State::S1;
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else if (sig.is_fully_const())
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ret = RTLIL::State::S0;
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else
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log_cmd_error("Cell port SigSpec has unexpected type.\n");
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//Finally, if the cell port was a module input or output, make sure the corresponding taint signal is marked, too:
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if(sig.is_wire() && sig.as_wire()->port_input)
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ret.as_wire()->port_input = true;
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if(sig.is_wire() && sig.as_wire()->port_output)
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new_taint_outputs.push_back(ret.as_wire());
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return ret;
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}
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void add_precise_GLIFT_logic(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
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//AKA AN2_SH2 or OR2_SH2
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RTLIL::SigSpec n_port_a = module->LogicNot(cell->name.str() + "_t_1_1", port_a, false, cell->get_src_attribute());
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RTLIL::SigSpec n_port_b = module->LogicNot(cell->name.str() + "_t_1_2", port_b, false, cell->get_src_attribute());
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auto subexpr1 = module->And(cell->name.str() + "_t_1_3", (cell->type == "$_AND_")? port_a : n_port_a, port_b_taint, false, cell->get_src_attribute());
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auto subexpr2 = module->And(cell->name.str() + "_t_1_4", (cell->type == "$_AND_")? port_b : n_port_b, port_a_taint, false, cell->get_src_attribute());
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auto subexpr3 = module->And(cell->name.str() + "_t_1_5", port_a_taint, port_b_taint, false, cell->get_src_attribute());
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auto subexpr4 = module->Or(cell->name.str() + "_t_1_6", subexpr1, subexpr2, false, cell->get_src_attribute());
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module->addOr(cell->name.str() + "_t_1_7", subexpr4, subexpr3, port_y_taint, false, cell->get_src_attribute());
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}
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void add_imprecise_GLIFT_logic_1(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
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//AKA AN2_SH3 or OR2_SH3
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RTLIL::SigSpec n_port_a = module->LogicNot(cell->name.str() + "_t_2_1", port_a, false, cell->get_src_attribute());
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auto subexpr1 = module->And(cell->name.str() + "_t_2_2", (cell->type == "$_AND_")? port_b : n_port_a, (cell->type == "$_AND_")? port_a_taint : port_b_taint, false, cell->get_src_attribute());
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module->addOr(cell->name.str() + "_t_2_3", (cell->type == "$_AND_")? port_b_taint : port_a_taint, subexpr1, port_y_taint, false, cell->get_src_attribute());
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}
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void add_imprecise_GLIFT_logic_2(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
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//AKA AN2_SH4 or OR2_SH4
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RTLIL::SigSpec n_port_b = module->LogicNot(cell->name.str() + "_t_3_1", port_b, false, cell->get_src_attribute());
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auto subexpr1 = module->And(cell->name.str() + "_t_3_2", (cell->type == "$_AND_")? port_a : n_port_b, (cell->type == "$_AND_")? port_b_taint : port_a_taint, false, cell->get_src_attribute());
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module->addOr(cell->name.str() + "_t_3_3", (cell->type == "$_AND_")? port_a_taint : port_b_taint, subexpr1, port_y_taint, false, cell->get_src_attribute());
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}
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void add_imprecise_GLIFT_logic_3(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) {
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//AKA AN2_SH5 or OR2_SH5
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module->addOr(cell->name.str() + "_t_4_1", port_a_taint, port_b_taint, port_y_taint, false, cell->get_src_attribute());
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}
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RTLIL::SigSpec score_metamux_select(const RTLIL::SigSpec &metamux_select) {
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log_assert(metamux_select.is_wire());
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log_assert(metamux_select.as_wire()->width == 2);
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RTLIL::Const precise_y_cost(5); //5 AND/OR gates
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RTLIL::Const imprecise_1_y_cost(2);
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RTLIL::Const imprecise_2_y_cost(2);
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RTLIL::Const imprecise_3_y_cost(1);
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RTLIL::SigSpec meta_mux1 = module->Pmux(metamux_select.as_wire()->name.str() + "_mux1", precise_y_cost, imprecise_1_y_cost, metamux_select[1], metamux_select.as_wire()->get_src_attribute());
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RTLIL::SigSpec meta_mux2 = module->Pmux(metamux_select.as_wire()->name.str() + "_mux2", imprecise_2_y_cost, imprecise_3_y_cost, metamux_select[1], metamux_select.as_wire()->get_src_attribute());
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RTLIL::SigSpec ret = module->Pmux(metamux_select.as_wire()->name.str() + "_mux3", meta_mux1, meta_mux2, metamux_select[0], metamux_select.as_wire()->get_src_attribute());
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return ret;
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}
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void create_glift_logic() {
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std::vector<RTLIL::SigSig> connections(module->connections());
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std::vector<RTLIL::SigSig> new_connections;
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for(auto &cell : module->cells().to_vector()) {
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if (!cell->type.in("$_AND_", "$_OR_", "$_NOT_", "$anyconst", "$allconst", "$assume", "$assert")) {
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log_cmd_error("Invalid cell type \"%s\" found. Module must be techmapped.\n", cell->type.c_str());
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}
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if (cell->type.in("$_AND_", "$_OR_")) {
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const unsigned int A = 0, B = 1, Y = 2;
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const unsigned int NUM_PORTS = 3;
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RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::Y)};
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RTLIL::SigSpec port_taints[NUM_PORTS];
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if (ports[A].size() != 1 || ports[B].size() != 1 || ports[Y].size() != 1)
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log_cmd_error("Multi-bit signal found. Run `splitnets` first.\n");
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for (unsigned int i = 0; i < NUM_PORTS; ++i)
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port_taints[i] = get_corresponding_taint_signal(ports[i]);
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if (opt_create)
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add_precise_GLIFT_logic(cell, ports[A], port_taints[A], ports[B], port_taints[B], port_taints[Y]);
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else if (opt_sketchify) {
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RTLIL::SigSpec precise_y(module->addWire(cell->name.str() + "_y1", 1)),
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imprecise_1_y(module->addWire(cell->name.str() + "_y2", 1)),
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imprecise_2_y(module->addWire(cell->name.str() + "_y3", 1)),
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imprecise_3_y(module->addWire(cell->name.str() + "_y4", 1));
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add_precise_GLIFT_logic(cell, ports[A], port_taints[A], ports[B], port_taints[B], precise_y);
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add_imprecise_GLIFT_logic_1(cell, ports[A], port_taints[A], ports[B], port_taints[B], imprecise_1_y);
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add_imprecise_GLIFT_logic_2(cell, ports[A], port_taints[A], ports[B], port_taints[B], imprecise_2_y);
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add_imprecise_GLIFT_logic_3(cell, port_taints[A], port_taints[B], imprecise_3_y);
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RTLIL::SigSpec meta_mux_select(module->addWire(cell->name.str() + "_sel", 2));
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meta_mux_selects.push_back(meta_mux_select);
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new_connections.emplace_back(meta_mux_select, module->Anyconst(cell->name.str() + "_hole", 2, cell->get_src_attribute()));
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RTLIL::SigSpec meta_mux1(module->Mux(cell->name.str() + "_mux1", precise_y, imprecise_1_y, meta_mux_select[1]));
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RTLIL::SigSpec meta_mux2(module->Mux(cell->name.str() + "_mux2", imprecise_2_y, imprecise_3_y, meta_mux_select[1]));
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module->addMux(cell->name.str() + "_mux3", meta_mux1, meta_mux2, meta_mux_select[0], port_taints[Y]);
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}
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else log_cmd_error("This is a bug (1).\n");
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}
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else if (cell->type.in("$_NOT_")) {
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const unsigned int A = 0, Y = 1;
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const unsigned int NUM_PORTS = 2;
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RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::Y)};
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RTLIL::SigSpec port_taints[NUM_PORTS];
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if (ports[A].size() != 1 || ports[Y].size() != 1)
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log_cmd_error("Multi-bit signal found. Run `splitnets` first.\n");
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for (unsigned int i = 0; i < NUM_PORTS; ++i)
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port_taints[i] = get_corresponding_taint_signal(ports[i]);
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if (cell->type == "$_NOT_") {
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new_connections.emplace_back(port_taints[Y], port_taints[A]);
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}
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else log_cmd_error("This is a bug (2).\n");
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}
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} //end foreach cell in cells
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for (auto &conn : connections) {
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RTLIL::SigSpec first = get_corresponding_taint_signal(conn.first);
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RTLIL::SigSpec second = get_corresponding_taint_signal(conn.second);
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module->connect(get_corresponding_taint_signal(conn.first), get_corresponding_taint_signal(conn.second));
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if(conn.second.is_wire() && conn.second.as_wire()->port_input)
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second.as_wire()->port_input = true;
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if(conn.first.is_wire() && conn.first.as_wire()->port_output)
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new_taint_outputs.push_back(first.as_wire());
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} //end foreach conn in connections
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//Create a rough model of area by summing the "weight" score of each meta-mux select:
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if (!opt_nomodeloptimize) {
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std::vector<RTLIL::SigSpec> meta_mux_select_sums;
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std::vector<RTLIL::SigSpec> meta_mux_select_sums_buf;
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for (auto &wire : meta_mux_selects) {
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meta_mux_select_sums.emplace_back(score_metamux_select(wire));
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}
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for (unsigned int i = 0; meta_mux_select_sums.size() > 1; ) {
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meta_mux_select_sums_buf.clear();
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for (i = 0; i + 1 < meta_mux_select_sums.size(); i += 2) {
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meta_mux_select_sums_buf.push_back(module->Add(meta_mux_select_sums[i].as_wire()->name.str() + "_add", meta_mux_select_sums[i], meta_mux_select_sums[i+1], false));
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}
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if (meta_mux_select_sums.size() % 2 == 1)
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meta_mux_select_sums_buf.push_back(meta_mux_select_sums[meta_mux_select_sums.size()-1]);
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meta_mux_select_sums.swap(meta_mux_select_sums_buf);
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}
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if (meta_mux_select_sums.size() > 0) {
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meta_mux_select_sums[0].as_wire()->set_bool_attribute("\\minimize");
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meta_mux_select_sums[0].as_wire()->set_bool_attribute("\\keep");
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module->rename(meta_mux_select_sums[0].as_wire(), ID(__glift_weight));
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}
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}
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//Add new connections and mark new module outputs:
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for (auto &conn : new_connections)
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module->connect(conn);
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for (auto &port_name : module->ports) {
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RTLIL::Wire *port = module->wire(port_name);
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log_assert(port != nullptr);
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if (port->port_output && !opt_keepoutputs)
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port->port_output = false;
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}
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for (auto &output : new_taint_outputs)
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output->port_output = true;
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module->fixup_ports(); //we have some new taint signals in the module interface
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}
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void reset() {
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opt_create = false;
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opt_sketchify = false;
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opt_taintconstants = false;
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opt_keepoutputs = false;
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opt_nomodeloptimize = false;
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module = nullptr;
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args.clear();
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argidx = 0;
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new_taint_outputs.clear();
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meta_mux_selects.clear();
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}
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public:
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GliftPass() : Pass("glift", "create and transform GLIFT models"), opt_create(false), opt_sketchify(false), opt_taintconstants(false), opt_keepoutputs(false), opt_nomodeloptimize(false), module(nullptr) { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" glift -create|-sketchify [options] [selection]\n");
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log("\n");
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log("Adds, removes, or manipulates gate-level information flow tracking (GLIFT) logic\n");
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log("to the current or specified module.\n");
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log("\n");
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log("Commands:\n");
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log("\n");
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log(" -create\n");
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log(" Replaces the current or specified module with one that has additional \"taint\"\n");
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log(" inputs, outputs, and internal nets along with precise taint-tracking logic.\n");
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log("\n");
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log(" -sketchify\n");
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log(" Replaces the current or specified module with one that has additional \"taint\"\n");
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log(" inputs, outputs, and internal nets along with varying-precision taint-tracking logic.\n");
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log(" Which version of taint tracking logic is used at a given cell is determined by a MUX\n");
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log(" selected by an $anyconst cell.\n");
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log("\n");
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log("Options:\n");
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log("\n");
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log(" -taint-constants\n");
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log(" Constant values in the design are labeled as tainted.\n");
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log(" (default: label constants as un-tainted)\n");
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log("\n");
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log(" -keep-outputs\n");
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log(" Do not remove module outputs. Taint tracking outputs will appear in the module ports\n");
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log(" alongside the orignal outputs.\n");
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log(" (default: original module outputs are removed)\n");
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log("\n");
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log(" -no-model-optimize\n");
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log(" Do not model imprecise taint tracking logic area and attempt to minimize it.\n");
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log(" (default: model area and give that signal the \"minimize\" attribute)\n");
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log("\n");
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}
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void execute(std::vector<std::string> _args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing GLIFT pass (creating and manipulating GLIFT models).\n");
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reset();
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args = _args;
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parse_args();
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extra_args(args, argidx, design);
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for (auto mod : design->selected_modules()) {
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if (module)
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log_cmd_error("Only one module may be selected for the glift pass! Flatten the design if necessary. (selected: %s and %s)\n", log_id(module), log_id(mod));
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module = mod;
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}
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if (module == nullptr)
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log_cmd_error("Can't operate on an empty selection!\n");
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create_glift_logic();
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}
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} GliftPass;
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PRIVATE_NAMESPACE_END
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