mirror of https://github.com/YosysHQ/yosys.git
53 lines
1.7 KiB
Verilog
53 lines
1.7 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// ============================================================================
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(* techmap_celltype = "$__ABC9_ASYNC0 $__ABC9_ASYNC1" *)
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module $__ABC9_ASYNC01(input A, S, output Y);
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assign Y = A;
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endmodule
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module $__ABC9_FF_(input D, output Q);
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assign Q = D;
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endmodule
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module $__ABC9_LUT6(input A, input [5:0] S, output Y);
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assign Y = A;
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endmodule
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module $__ABC9_LUT7(input A, input [6:0] S, output Y);
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assign Y = A;
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endmodule
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(* techmap_celltype = "$__ABC9_DSP48E1_MULT $__ABC9_DSP48E1_MULT_DPORT $__ABC9_DSP48E1" *)
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module $ABC9_DSP48E1(
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input [29:0] $A,
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input [17:0] $B,
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input [47:0] $C,
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input [24:0] $D,
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input [47:0] $P,
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input [47:0] $PCIN,
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input [47:0] $PCOUT,
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output [47:0] P,
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output [47:0] PCOUT
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);
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assign P = $P, PCOUT = $PCOUT;
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endmodule
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