yosys/manual/PRESENTATION_ExAdv/macc_simple_test_02.v

7 lines
127 B
Verilog

module test(a, b, c, d, x, y);
input [15:0] a, b, c, d;
input [31:0] x;
output [31:0] y;
assign y = a*b + (c*d + x);
endmodule