mirror of https://github.com/YosysHQ/yosys.git
98 lines
1.6 KiB
Verilog
98 lines
1.6 KiB
Verilog
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module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter [31:0] INIT = 32'bx;
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parameter CLKPOL2 = 1;
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input CLK1;
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input [4:0] A1ADDR;
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output A1DATA;
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input [4:0] B1ADDR;
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input B1DATA;
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input B1EN;
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RAM32X1D #(
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.INIT(INIT),
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.IS_WCLK_INVERTED(!CLKPOL2)
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) _TECHMAP_REPLACE_ (
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.DPRA0(A1ADDR[0]),
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.DPRA1(A1ADDR[1]),
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.DPRA2(A1ADDR[2]),
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.DPRA3(A1ADDR[3]),
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.DPRA4(A1ADDR[4]),
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.DPO(A1DATA),
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.A0(B1ADDR[0]),
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.A1(B1ADDR[1]),
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.A2(B1ADDR[2]),
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.A3(B1ADDR[3]),
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.A4(B1ADDR[4]),
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.D(B1DATA),
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.WCLK(CLK1),
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.WE(B1EN)
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);
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endmodule
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module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter [63:0] INIT = 64'bx;
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parameter CLKPOL2 = 1;
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input CLK1;
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input [5:0] A1ADDR;
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output A1DATA;
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input [5:0] B1ADDR;
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input B1DATA;
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input B1EN;
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RAM64X1D #(
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.INIT(INIT),
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.IS_WCLK_INVERTED(!CLKPOL2)
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) _TECHMAP_REPLACE_ (
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.DPRA0(A1ADDR[0]),
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.DPRA1(A1ADDR[1]),
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.DPRA2(A1ADDR[2]),
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.DPRA3(A1ADDR[3]),
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.DPRA4(A1ADDR[4]),
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.DPRA5(A1ADDR[5]),
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.DPO(A1DATA),
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.A0(B1ADDR[0]),
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.A1(B1ADDR[1]),
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.A2(B1ADDR[2]),
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.A3(B1ADDR[3]),
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.A4(B1ADDR[4]),
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.A5(B1ADDR[5]),
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.D(B1DATA),
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.WCLK(CLK1),
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.WE(B1EN)
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);
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endmodule
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module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter [127:0] INIT = 128'bx;
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parameter CLKPOL2 = 1;
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input CLK1;
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input [6:0] A1ADDR;
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output A1DATA;
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input [6:0] B1ADDR;
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input B1DATA;
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input B1EN;
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RAM128X1D #(
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.INIT(INIT),
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.IS_WCLK_INVERTED(!CLKPOL2)
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) _TECHMAP_REPLACE_ (
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.DPRA(A1ADDR),
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.DPO(A1DATA),
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.A(B1ADDR),
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.D(B1DATA),
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.WCLK(CLK1),
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.WE(B1EN)
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);
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endmodule
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