mirror of https://github.com/YosysHQ/yosys.git
83 lines
2.0 KiB
Verilog
83 lines
2.0 KiB
Verilog
`ifdef cyclonev
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`define LCELL cyclonev_lcell_comb
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`endif
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`ifdef cyclone10gx
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`define LCELL cyclone10gx_lcell_comb
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`endif
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module __MISTRAL_VCC(output Q);
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MISTRAL_ALUT2 #(.LUT(4'b1111)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
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endmodule
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module __MISTRAL_GND(output Q);
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MISTRAL_ALUT2 #(.LUT(4'b0000)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
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endmodule
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module MISTRAL_FF(input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA, output reg Q);
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dffeas #(.power_up("low"), .is_wysiwyg("true")) _TECHMAP_REPLACE_ (.d(DATAIN), .clk(CLK), .clrn(ACLR), .ena(ENA), .sclr(SCLR), .sload(SLOAD), .asdata(SDATA), .q(Q));
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endmodule
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module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
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parameter [63:0] LUT = 64'h0000_0000_0000_0000;
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`LCELL #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
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endmodule
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module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
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parameter [31:0] LUT = 32'h0000_0000;
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`LCELL #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
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endmodule
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module MISTRAL_ALUT4(input A, B, C, D, output Q);
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parameter [15:0] LUT = 16'h0000;
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`LCELL #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
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endmodule
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module MISTRAL_ALUT3(input A, B, C, output Q);
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parameter [7:0] LUT = 8'h00;
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`LCELL #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
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endmodule
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module MISTRAL_ALUT2(input A, B, output Q);
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parameter [3:0] LUT = 4'h0;
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`LCELL #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
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endmodule
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module MISTRAL_NOT(input A, output Q);
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NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
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endmodule
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module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
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parameter LUT0 = 16'h0000;
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parameter LUT1 = 16'h0000;
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`LCELL #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
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endmodule
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