mirror of https://github.com/YosysHQ/yosys.git
536 lines
16 KiB
C++
536 lines
16 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <assert.h>
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#include <stdio.h>
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#include <string.h>
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extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
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static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\Y_WIDTH").as_int();
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RTLIL::SigSpec sig_a = cell->connections.at("\\A");
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sig_a.extend(width, cell->parameters.at("\\A_SIGNED").as_bool());
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sig_a.expand();
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RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
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sig_y.expand();
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = new RTLIL::Cell;
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gate->name = NEW_ID;
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gate->type = "$_INV_";
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gate->connections["\\A"] = sig_a.chunks.at(i);
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gate->connections["\\Y"] = sig_y.chunks.at(i);
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module->add(gate);
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}
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}
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static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\Y_WIDTH").as_int();
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RTLIL::SigSpec sig_a = cell->connections.at("\\A");
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sig_a.extend(width, cell->parameters.at("\\A_SIGNED").as_bool());
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RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
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module->connections.push_back(RTLIL::SigSig(sig_y, sig_a));
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}
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static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\Y_WIDTH").as_int();
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RTLIL::SigSpec sig_a = cell->connections.at("\\A");
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sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool());
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RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
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module->connections.push_back(RTLIL::SigSig(sig_y, sig_a));
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}
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static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\Y_WIDTH").as_int();
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RTLIL::SigSpec sig_a = cell->connections.at("\\A");
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sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool());
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sig_a.expand();
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RTLIL::SigSpec sig_b = cell->connections.at("\\B");
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sig_b.extend_u0(width, cell->parameters.at("\\B_SIGNED").as_bool());
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sig_b.expand();
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RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
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sig_y.expand();
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if (cell->type == "$xnor")
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{
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RTLIL::SigSpec sig_t = module->new_wire(width, NEW_ID);
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sig_t.expand();
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = new RTLIL::Cell;
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gate->name = NEW_ID;
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gate->type = "$_INV_";
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gate->connections["\\A"] = sig_t.chunks.at(i);
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gate->connections["\\Y"] = sig_y.chunks.at(i);
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module->add(gate);
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}
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sig_y = sig_t;
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}
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std::string gate_type;
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if (cell->type == "$and") gate_type = "$_AND_";
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if (cell->type == "$or") gate_type = "$_OR_";
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if (cell->type == "$xor") gate_type = "$_XOR_";
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if (cell->type == "$xnor") gate_type = "$_XOR_";
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log_assert(!gate_type.empty());
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = new RTLIL::Cell;
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gate->name = NEW_ID;
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gate->type = gate_type;
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gate->connections["\\A"] = sig_a.chunks.at(i);
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gate->connections["\\B"] = sig_b.chunks.at(i);
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gate->connections["\\Y"] = sig_y.chunks.at(i);
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module->add(gate);
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}
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}
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static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->connections.at("\\A");
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sig_a.expand();
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RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
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if (sig_y.width == 0)
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return;
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if (sig_a.width == 0) {
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if (cell->type == "$reduce_and") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.width)));
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if (cell->type == "$reduce_or") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.width)));
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if (cell->type == "$reduce_xor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.width)));
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if (cell->type == "$reduce_xnor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.width)));
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if (cell->type == "$reduce_bool") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.width)));
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return;
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}
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if (sig_y.width > 1) {
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module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.width-1), RTLIL::SigSpec(0, sig_y.width-1)));
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sig_y = sig_y.extract(0, 1);
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}
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std::string gate_type;
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if (cell->type == "$reduce_and") gate_type = "$_AND_";
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if (cell->type == "$reduce_or") gate_type = "$_OR_";
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if (cell->type == "$reduce_xor") gate_type = "$_XOR_";
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if (cell->type == "$reduce_xnor") gate_type = "$_XOR_";
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if (cell->type == "$reduce_bool") gate_type = "$_OR_";
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log_assert(!gate_type.empty());
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RTLIL::SigSpec *last_output = NULL;
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while (sig_a.width > 1)
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{
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RTLIL::SigSpec sig_t = module->new_wire(sig_a.width / 2, NEW_ID);
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sig_t.expand();
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for (int i = 0; i < sig_a.width; i += 2)
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{
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if (i+1 == sig_a.width) {
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sig_t.append(sig_a.chunks.at(i));
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continue;
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}
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RTLIL::Cell *gate = new RTLIL::Cell;
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gate->name = NEW_ID;
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gate->type = gate_type;
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gate->connections["\\A"] = sig_a.chunks.at(i);
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gate->connections["\\B"] = sig_a.chunks.at(i+1);
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gate->connections["\\Y"] = sig_t.chunks.at(i/2);
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last_output = &gate->connections["\\Y"];
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module->add(gate);
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}
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sig_a = sig_t;
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}
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if (cell->type == "$reduce_xnor") {
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RTLIL::SigSpec sig_t = module->new_wire(1, NEW_ID);
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RTLIL::Cell *gate = new RTLIL::Cell;
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gate->name = NEW_ID;
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gate->type = "$_INV_";
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gate->connections["\\A"] = sig_a;
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gate->connections["\\Y"] = sig_t;
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last_output = &gate->connections["\\Y"];
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module->add(gate);
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sig_a = sig_t;
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}
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if (last_output == NULL) {
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module->connections.push_back(RTLIL::SigSig(sig_y, sig_a));
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} else {
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*last_output = sig_y;
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}
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}
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static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
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{
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sig.expand();
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while (sig.width > 1)
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{
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RTLIL::SigSpec sig_t = module->new_wire(sig.width / 2, NEW_ID);
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sig_t.expand();
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for (int i = 0; i < sig.width; i += 2)
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{
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if (i+1 == sig.width) {
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sig_t.append(sig.chunks.at(i));
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continue;
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}
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RTLIL::Cell *gate = new RTLIL::Cell;
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gate->name = NEW_ID;
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gate->type = "$_OR_";
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gate->connections["\\A"] = sig.chunks.at(i);
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gate->connections["\\B"] = sig.chunks.at(i+1);
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gate->connections["\\Y"] = sig_t.chunks.at(i/2);
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module->add(gate);
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}
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sig = sig_t;
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}
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if (sig.width == 0)
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sig = RTLIL::SigSpec(0, 1);
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}
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static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->connections.at("\\A");
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logic_reduce(module, sig_a);
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RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
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if (sig_y.width == 0)
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return;
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if (sig_y.width > 1) {
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module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.width-1), RTLIL::SigSpec(0, sig_y.width-1)));
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sig_y = sig_y.extract(0, 1);
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}
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RTLIL::Cell *gate = new RTLIL::Cell;
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gate->name = NEW_ID;
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gate->type = "$_INV_";
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gate->connections["\\A"] = sig_a;
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gate->connections["\\Y"] = sig_y;
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module->add(gate);
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}
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static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->connections.at("\\A");
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logic_reduce(module, sig_a);
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RTLIL::SigSpec sig_b = cell->connections.at("\\B");
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logic_reduce(module, sig_b);
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RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
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if (sig_y.width == 0)
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return;
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if (sig_y.width > 1) {
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module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.width-1), RTLIL::SigSpec(0, sig_y.width-1)));
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sig_y = sig_y.extract(0, 1);
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}
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std::string gate_type;
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if (cell->type == "$logic_and") gate_type = "$_AND_";
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if (cell->type == "$logic_or") gate_type = "$_OR_";
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log_assert(!gate_type.empty());
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RTLIL::Cell *gate = new RTLIL::Cell;
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gate->name = NEW_ID;
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gate->type = gate_type;
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gate->connections["\\A"] = sig_a;
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gate->connections["\\B"] = sig_b;
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gate->connections["\\Y"] = sig_y;
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module->add(gate);
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}
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static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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RTLIL::SigSpec sig_a = cell->connections.at("\\A");
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sig_a.expand();
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RTLIL::SigSpec sig_b = cell->connections.at("\\B");
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sig_b.expand();
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RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
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sig_y.expand();
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = new RTLIL::Cell;
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gate->name = NEW_ID;
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gate->type = "$_MUX_";
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gate->connections["\\A"] = sig_a.chunks.at(i);
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gate->connections["\\B"] = sig_b.chunks.at(i);
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gate->connections["\\S"] = cell->connections.at("\\S");
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gate->connections["\\Y"] = sig_y.chunks.at(i);
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module->add(gate);
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}
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}
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static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
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char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
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RTLIL::SigSpec sig_s = cell->connections.at("\\SET");
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sig_s.expand();
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RTLIL::SigSpec sig_r = cell->connections.at("\\CLR");
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sig_r.expand();
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RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
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sig_q.expand();
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std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = new RTLIL::Cell;
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gate->name = NEW_ID;
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gate->type = gate_type;
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gate->connections["\\S"] = sig_s.chunks.at(i);
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gate->connections["\\R"] = sig_r.chunks.at(i);
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gate->connections["\\Q"] = sig_q.chunks.at(i);
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module->add(gate);
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}
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}
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static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
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RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK");
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RTLIL::SigSpec sig_d = cell->connections.at("\\D");
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sig_d.expand();
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RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
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sig_q.expand();
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std::string gate_type = stringf("$_DFF_%c_", clk_pol);
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = new RTLIL::Cell;
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gate->name = NEW_ID;
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gate->type = gate_type;
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gate->connections["\\C"] = sig_clk;
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gate->connections["\\D"] = sig_d.chunks.at(i);
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gate->connections["\\Q"] = sig_q.chunks.at(i);
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module->add(gate);
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}
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}
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static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
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char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
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char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
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RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK");
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RTLIL::SigSpec sig_s = cell->connections.at("\\SET");
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sig_s.expand();
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RTLIL::SigSpec sig_r = cell->connections.at("\\CLR");
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sig_r.expand();
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RTLIL::SigSpec sig_d = cell->connections.at("\\D");
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sig_d.expand();
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RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
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sig_q.expand();
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std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = new RTLIL::Cell;
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gate->name = NEW_ID;
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gate->type = gate_type;
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gate->connections["\\C"] = sig_clk;
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gate->connections["\\S"] = sig_s.chunks.at(i);
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gate->connections["\\R"] = sig_r.chunks.at(i);
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gate->connections["\\D"] = sig_d.chunks.at(i);
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gate->connections["\\Q"] = sig_q.chunks.at(i);
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module->add(gate);
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}
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}
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static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
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char rst_pol = cell->parameters.at("\\ARST_POLARITY").as_bool() ? 'P' : 'N';
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std::vector<RTLIL::State> rst_val = cell->parameters.at("\\ARST_VALUE").bits;
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while (int(rst_val.size()) < width)
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rst_val.push_back(RTLIL::State::S0);
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RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK");
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RTLIL::SigSpec sig_rst = cell->connections.at("\\ARST");
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RTLIL::SigSpec sig_d = cell->connections.at("\\D");
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sig_d.expand();
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RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
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sig_q.expand();
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std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
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std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = new RTLIL::Cell;
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gate->name = NEW_ID;
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gate->type = rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0;
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gate->connections["\\C"] = sig_clk;
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gate->connections["\\R"] = sig_rst;
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gate->connections["\\D"] = sig_d.chunks.at(i);
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gate->connections["\\Q"] = sig_q.chunks.at(i);
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module->add(gate);
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}
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}
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static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
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RTLIL::SigSpec sig_en = cell->connections.at("\\EN");
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|
RTLIL::SigSpec sig_d = cell->connections.at("\\D");
|
|
sig_d.expand();
|
|
|
|
RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
|
|
sig_q.expand();
|
|
|
|
std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
|
|
|
|
for (int i = 0; i < width; i++) {
|
|
RTLIL::Cell *gate = new RTLIL::Cell;
|
|
gate->name = NEW_ID;
|
|
gate->type = gate_type;
|
|
gate->connections["\\E"] = sig_en;
|
|
gate->connections["\\D"] = sig_d.chunks.at(i);
|
|
gate->connections["\\Q"] = sig_q.chunks.at(i);
|
|
module->add(gate);
|
|
}
|
|
}
|
|
|
|
void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
|
|
{
|
|
mappers["$not"] = simplemap_not;
|
|
mappers["$pos"] = simplemap_pos;
|
|
mappers["$bu0"] = simplemap_bu0;
|
|
mappers["$and"] = simplemap_bitop;
|
|
mappers["$or"] = simplemap_bitop;
|
|
mappers["$xor"] = simplemap_bitop;
|
|
mappers["$xnor"] = simplemap_bitop;
|
|
mappers["$reduce_and"] = simplemap_reduce;
|
|
mappers["$reduce_or"] = simplemap_reduce;
|
|
mappers["$reduce_xor"] = simplemap_reduce;
|
|
mappers["$reduce_xnor"] = simplemap_reduce;
|
|
mappers["$reduce_bool"] = simplemap_reduce;
|
|
mappers["$logic_not"] = simplemap_lognot;
|
|
mappers["$logic_and"] = simplemap_logbin;
|
|
mappers["$logic_or"] = simplemap_logbin;
|
|
mappers["$mux"] = simplemap_mux;
|
|
mappers["$sr"] = simplemap_sr;
|
|
mappers["$dff"] = simplemap_dff;
|
|
mappers["$dffsr"] = simplemap_dffsr;
|
|
mappers["$adff"] = simplemap_adff;
|
|
mappers["$dlatch"] = simplemap_dlatch;
|
|
}
|
|
|
|
struct SimplemapPass : public Pass {
|
|
SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
|
|
virtual void help()
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" simplemap [selection]\n");
|
|
log("\n");
|
|
log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
|
|
log("primitives. The following internal cell types are mapped by this pass:\n");
|
|
log("\n");
|
|
log(" $not, $pos, $bu0, $and, $or, $xor, $xnor\n");
|
|
log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
|
|
log(" $logic_not, $logic_and, $logic_or, $mux\n");
|
|
log(" $sr, $dff, $dffsr, $adff, $dlatch\n");
|
|
log("\n");
|
|
}
|
|
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
|
|
{
|
|
log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
|
|
extra_args(args, 1, design);
|
|
|
|
std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
|
|
simplemap_get_mappers(mappers);
|
|
|
|
for (auto &mod_it : design->modules) {
|
|
if (!design->selected(mod_it.second))
|
|
continue;
|
|
std::vector<RTLIL::Cell*> delete_cells;
|
|
for (auto &cell_it : mod_it.second->cells) {
|
|
if (mappers.count(cell_it.second->type) == 0)
|
|
continue;
|
|
if (!design->selected(mod_it.second, cell_it.second))
|
|
continue;
|
|
log("Mapping %s.%s (%s).\n", RTLIL::id2cstr(mod_it.first), RTLIL::id2cstr(cell_it.first), RTLIL::id2cstr(cell_it.second->type));
|
|
mappers.at(cell_it.second->type)(mod_it.second, cell_it.second);
|
|
delete_cells.push_back(cell_it.second);
|
|
}
|
|
for (auto &it : delete_cells) {
|
|
mod_it.second->cells.erase(it->name);
|
|
delete it;
|
|
}
|
|
}
|
|
}
|
|
} SimplemapPass;
|
|
|