mirror of https://github.com/YosysHQ/yosys.git
474 lines
14 KiB
C++
474 lines
14 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/consteval.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/satgen.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <algorithm>
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namespace {
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bool inv_mode;
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int verbose_level;
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typedef std::map<RTLIL::SigBit, std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>>> drivers_t;
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struct equiv_bit_t
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{
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int depth;
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bool inverted;
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RTLIL::SigBit bit;
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bool operator<(const equiv_bit_t &other) const {
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if (depth != other.depth)
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return depth < other.depth;
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if (inverted != other.inverted)
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return inverted < other.inverted;
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return bit < other.bit;
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}
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};
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struct FindReducedInputs
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{
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SigMap &sigmap;
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drivers_t &drivers;
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ezDefaultSAT ez;
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std::set<RTLIL::Cell*> ez_cells;
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SatGen satgen;
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FindReducedInputs(SigMap &sigmap, drivers_t &drivers) :
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sigmap(sigmap), drivers(drivers), satgen(&ez, &sigmap)
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{
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satgen.model_undef = true;
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}
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void register_cone_worker(std::set<RTLIL::SigBit> &pi, std::set<RTLIL::SigBit> &sigdone, RTLIL::SigBit out)
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{
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if (out.wire == NULL)
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return;
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if (sigdone.count(out) != 0)
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return;
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sigdone.insert(out);
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if (drivers.count(out) != 0) {
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std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(out);
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if (ez_cells.count(drv.first) == 0) {
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satgen.setContext(&sigmap, "A");
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if (!satgen.importCell(drv.first))
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log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type));
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satgen.setContext(&sigmap, "B");
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if (!satgen.importCell(drv.first))
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log_abort();
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ez_cells.insert(drv.first);
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}
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for (auto &bit : drv.second)
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register_cone_worker(pi, sigdone, bit);
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} else
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pi.insert(out);
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}
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void register_cone(std::vector<RTLIL::SigBit> &pi, RTLIL::SigBit out)
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{
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std::set<RTLIL::SigBit> pi_set, sigdone;
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register_cone_worker(pi_set, sigdone, out);
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pi.clear();
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pi.insert(pi.end(), pi_set.begin(), pi_set.end());
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}
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void analyze(std::vector<RTLIL::SigBit> &reduced_inputs, RTLIL::SigBit output)
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{
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if (verbose_level >= 1)
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log(" Analyzing input cone for signal %s:\n", log_signal(output));
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std::vector<RTLIL::SigBit> pi;
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register_cone(pi, output);
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if (verbose_level >= 1)
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log(" Found %d input signals and %d cells.\n", int(pi.size()), int(ez_cells.size()));
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satgen.setContext(&sigmap, "A");
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int output_a = satgen.importSigSpec(output).front();
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int output_undef_a = satgen.importUndefSigSpec(output).front();
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ez.assume(ez.NOT(ez.expression(ezSAT::OpOr, satgen.importUndefSigSpec(pi))));
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satgen.setContext(&sigmap, "B");
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int output_b = satgen.importSigSpec(output).front();
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int output_undef_b = satgen.importUndefSigSpec(output).front();
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ez.assume(ez.NOT(ez.expression(ezSAT::OpOr, satgen.importUndefSigSpec(pi))));
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for (size_t i = 0; i < pi.size(); i++)
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{
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RTLIL::SigSpec test_sig(pi[i]);
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RTLIL::SigSpec rest_sig(pi);
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rest_sig.remove(i, 1);
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int test_sig_a, test_sig_b;
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std::vector<int> rest_sig_a, rest_sig_b;
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satgen.setContext(&sigmap, "A");
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test_sig_a = satgen.importSigSpec(test_sig).front();
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rest_sig_a = satgen.importSigSpec(rest_sig);
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satgen.setContext(&sigmap, "B");
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test_sig_b = satgen.importSigSpec(test_sig).front();
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rest_sig_b = satgen.importSigSpec(rest_sig);
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if (ez.solve(ez.vec_eq(rest_sig_a, rest_sig_b), ez.XOR(output_a, output_b), ez.XOR(test_sig_a, test_sig_b), ez.NOT(output_undef_a), ez.NOT(output_undef_b))) {
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if (verbose_level >= 2)
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log(" Result for input %s: pass\n", log_signal(test_sig));
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reduced_inputs.push_back(pi[i]);
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} else {
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if (verbose_level >= 2)
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log(" Result for input %s: strip\n", log_signal(test_sig));
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}
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}
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if (verbose_level >= 1)
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log(" Reduced input cone contains %d inputs.\n", int(reduced_inputs.size()));
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}
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};
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struct PerformReduction
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{
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SigMap &sigmap;
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drivers_t &drivers;
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std::set<std::pair<RTLIL::SigBit, RTLIL::SigBit>> &inv_pairs;
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ezDefaultSAT ez;
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SatGen satgen;
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std::vector<int> sat_pi, sat_out, sat_def;
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std::vector<RTLIL::SigBit> out_bits, pi_bits;
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std::vector<bool> out_inverted;
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std::vector<int> out_depth;
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int register_cone_worker(std::set<RTLIL::Cell*> &celldone, std::map<RTLIL::SigBit, int> &sigdepth, RTLIL::SigBit out)
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{
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if (out.wire == NULL)
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return 0;
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if (sigdepth.count(out) != 0)
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return sigdepth.at(out);
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sigdepth[out] = 0;
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if (drivers.count(out) != 0) {
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std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(out);
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if (celldone.count(drv.first) == 0) {
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if (!satgen.importCell(drv.first))
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log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type));
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celldone.insert(drv.first);
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}
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int max_child_dept = 0;
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for (auto &bit : drv.second)
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max_child_dept = std::max(register_cone_worker(celldone, sigdepth, bit), max_child_dept);
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sigdepth[out] = max_child_dept + 1;
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} else {
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pi_bits.push_back(out);
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sat_pi.push_back(satgen.importSigSpec(out).front());
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ez.assume(ez.NOT(satgen.importUndefSigSpec(out).front()));
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}
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return sigdepth[out];
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}
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PerformReduction(SigMap &sigmap, drivers_t &drivers, std::set<std::pair<RTLIL::SigBit, RTLIL::SigBit>> &inv_pairs, std::vector<RTLIL::SigBit> &bits) :
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sigmap(sigmap), drivers(drivers), inv_pairs(inv_pairs), satgen(&ez, &sigmap), out_bits(bits)
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{
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satgen.model_undef = true;
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std::set<RTLIL::Cell*> celldone;
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std::map<RTLIL::SigBit, int> sigdepth;
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for (auto &bit : bits) {
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out_depth.push_back(register_cone_worker(celldone, sigdepth, bit));
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sat_out.push_back(satgen.importSigSpec(bit).front());
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sat_def.push_back(ez.NOT(satgen.importUndefSigSpec(bit).front()));
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}
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if (inv_mode) {
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if (!ez.solve(sat_out, out_inverted, ez.expression(ezSAT::OpAnd, sat_def)))
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log_error("Solving for initial model failed!\n");
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for (size_t i = 0; i < sat_out.size(); i++)
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if (out_inverted.at(i))
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sat_out[i] = ez.NOT(sat_out[i]);
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} else
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out_inverted = std::vector<bool>(sat_out.size(), false);
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}
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void analyze(std::vector<std::vector<equiv_bit_t>> &results, std::vector<int> &bucket, int level)
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{
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if (bucket.size() <= 1)
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return;
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if (verbose_level >= 1)
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log("%*s Trying to shatter bucket with %d signals.\n", 2*level, "", int(bucket.size()));
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std::vector<int> sat_list, sat_inv_list;
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for (int idx : bucket) {
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sat_list.push_back(ez.AND(sat_out[idx], sat_def[idx]));
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sat_inv_list.push_back(ez.AND(ez.NOT(sat_out[idx]), sat_def[idx]));
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}
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std::vector<int> modelVars = sat_out;
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std::vector<bool> model;
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if (verbose_level >= 2) {
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modelVars.insert(modelVars.end(), sat_def.begin(), sat_def.end());
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modelVars.insert(modelVars.end(), sat_pi.begin(), sat_pi.end());
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}
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if (ez.solve(modelVars, model, ez.expression(ezSAT::OpOr, sat_list), ez.expression(ezSAT::OpOr, sat_inv_list)))
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{
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if (verbose_level >= 2) {
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for (size_t i = 0; i < pi_bits.size(); i++)
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log("%*s -> PI %c == %s\n", 2*level, "", model[2*sat_out.size() + i] ? '1' : '0', log_signal(pi_bits[i]));
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for (int idx : bucket)
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log("%*s -> OUT %c == %s%s\n", 2*level, "", model[sat_out.size() + idx] ? model[idx] ? '1' : '0' : 'x',
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out_inverted.at(idx) ? "~" : "", log_signal(out_bits[idx]));
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}
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std::vector<int> buckets[2];
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for (int idx : bucket)
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buckets[model[idx] ? 1 : 0].push_back(idx);
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analyze(results, buckets[0], level+1);
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analyze(results, buckets[1], level+1);
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}
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else
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{
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if (verbose_level >= 1) {
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log("%*s Found %d equivialent signals:", 2*level, "", int(bucket.size()));
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for (int idx : bucket)
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log("%s%s%s", idx == bucket.front() ? " " : ", ", out_inverted[idx] ? "~" : "", log_signal(out_bits[idx]));
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log("\n");
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}
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std::vector<equiv_bit_t> result;
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for (int idx : bucket) {
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equiv_bit_t bit;
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bit.depth = out_depth[idx];
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bit.inverted = out_inverted[idx];
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bit.bit = out_bits[idx];
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result.push_back(bit);
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}
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std::sort(result.begin(), result.end());
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if (result.front().inverted)
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for (auto &bit : result)
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bit.inverted = !bit.inverted;
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for (size_t i = 1; i < result.size(); i++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> p(result[0].bit, result[i].bit);
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if (inv_pairs.count(p) != 0)
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result.erase(result.begin() + i);
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}
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if (result.size() > 1)
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results.push_back(result);
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}
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}
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void analyze(std::vector<std::vector<equiv_bit_t>> &results)
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{
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std::vector<int> bucket;
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for (size_t i = 0; i < sat_out.size(); i++)
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bucket.push_back(i);
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analyze(results, bucket, 1);
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}
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};
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struct FreduceHelper
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{
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RTLIL::Module *module;
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SigMap sigmap;
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drivers_t drivers;
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std::set<std::pair<RTLIL::SigBit, RTLIL::SigBit>> inv_pairs;
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FreduceHelper(RTLIL::Module *module) : module(module), sigmap(module)
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{
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}
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int run()
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{
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log("Running functional reduction on module %s:\n", RTLIL::id2cstr(module->name));
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CellTypes ct;
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ct.setup_internals();
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ct.setup_stdcells();
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std::vector<std::set<RTLIL::SigBit>> batches;
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for (auto &it : module->cells) {
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if (ct.cell_known(it.second->type)) {
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std::set<RTLIL::SigBit> inputs, outputs;
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for (auto &port : it.second->connections) {
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std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
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if (ct.cell_output(it.second->type, port.first))
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outputs.insert(bits.begin(), bits.end());
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else
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inputs.insert(bits.begin(), bits.end());
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}
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std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(it.second, inputs);
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for (auto &bit : outputs)
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drivers[bit] = drv;
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batches.push_back(outputs);
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}
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if (inv_mode && it.second->type == "$_INV_")
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inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->connections.at("\\A")), sigmap(it.second->connections.at("\\Y"))));
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}
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int bits_count = 0;
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std::map<std::vector<RTLIL::SigBit>, std::vector<RTLIL::SigBit>> buckets;
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for (auto &batch : batches)
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{
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RTLIL::SigSpec batch_sig(std::vector<RTLIL::SigBit>(batch.begin(), batch.end()));
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batch_sig.optimize();
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log(" Finding reduced input cone for signal batch %s%c\n", log_signal(batch_sig), verbose_level ? ':' : '.');
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FindReducedInputs infinder(sigmap, drivers);
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for (auto &bit : batch) {
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std::vector<RTLIL::SigBit> inputs;
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infinder.analyze(inputs, bit);
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buckets[inputs].push_back(bit);
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bits_count++;
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}
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}
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log(" Sorted %d signal bits into %d buckets.\n", bits_count, int(buckets.size()));
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std::vector<std::vector<equiv_bit_t>> equiv;
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for (auto &bucket : buckets)
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{
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if (bucket.second.size() == 1)
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continue;
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RTLIL::SigSpec bucket_sig(bucket.second);
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bucket_sig.optimize();
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log(" Trying to shatter bucket %s%c\n", log_signal(bucket_sig), verbose_level ? ':' : '.');
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PerformReduction worker(sigmap, drivers, inv_pairs, bucket.second);
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worker.analyze(equiv);
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}
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log(" Rewiring %d equivialent groups:\n", int(equiv.size()));
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int rewired_sigbits = 0;
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for (auto &grp : equiv)
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{
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log(" Using as master for group: %s\n", log_signal(grp.front().bit));
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RTLIL::SigSpec inv_sig;
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for (size_t i = 1; i < grp.size(); i++)
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{
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log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit));
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RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
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RTLIL::Wire *dummy_wire = module->new_wire(1, NEW_ID);
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for (auto &port : drv->connections)
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sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
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if (grp[i].inverted)
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{
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if (inv_sig.width == 0)
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{
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inv_sig = module->new_wire(1, NEW_ID);
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RTLIL::Cell *inv_cell = new RTLIL::Cell;
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inv_cell->name = NEW_ID;
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inv_cell->type = "$_INV_";
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inv_cell->connections["\\A"] = grp[0].bit;
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inv_cell->connections["\\Y"] = inv_sig;
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module->add(inv_cell);
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}
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module->connections.push_back(RTLIL::SigSig(grp[i].bit, inv_sig));
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}
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else
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module->connections.push_back(RTLIL::SigSig(grp[i].bit, grp[0].bit));
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rewired_sigbits++;
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}
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}
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log(" Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, RTLIL::id2cstr(module->name));
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return rewired_sigbits;
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}
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};
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} /* namespace */
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struct FreducePass : public Pass {
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FreducePass() : Pass("freduce", "perform functional reduction") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" freduce [options] [selection]\n");
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log("\n");
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log("This pass performs functional reduction in the circuit. I.e. if two nodes are\n");
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log("equivialent, they are merged to one node and one of the redundant drivers is\n");
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log("removed.\n");
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log("\n");
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log(" -v, -vv\n");
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log(" enable verbose or very verbose output\n");
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log("\n");
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log(" -inv\n");
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log(" enable explicit handling of inverted signals\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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verbose_level = 0;
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inv_mode = false;
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log_header("Executing FREDUCE pass (perform functional reduction).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-v") {
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verbose_level = 1;
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continue;
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}
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if (args[argidx] == "-vv") {
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verbose_level = 2;
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continue;
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}
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if (args[argidx] == "-inv") {
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inv_mode = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
int bitcount = 0;
|
|
for (auto &mod_it : design->modules) {
|
|
RTLIL::Module *module = mod_it.second;
|
|
if (design->selected(module))
|
|
bitcount += FreduceHelper(module).run();
|
|
}
|
|
|
|
log("Rewired a total of %d signal bits.\n", bitcount);
|
|
}
|
|
} FreducePass;
|
|
|