mirror of https://github.com/YosysHQ/yosys.git
419 lines
14 KiB
C++
419 lines
14 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <fnmatch.h>
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#include <set>
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namespace {
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struct generate_port_decl_t {
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bool input, output;
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std::string portname;
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int index;
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};
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}
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static void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, const std::vector<generate_port_decl_t> &portdecls)
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{
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std::set<std::string> found_celltypes;
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for (auto i1 : design->modules)
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for (auto i2 : i1.second->cells)
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{
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RTLIL::Cell *cell = i2.second;
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if (cell->type[0] == '$' || design->modules.count(cell->type) > 0)
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continue;
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for (auto &pattern : celltypes)
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if (!fnmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str(), FNM_NOESCAPE))
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found_celltypes.insert(cell->type);
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}
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for (auto &celltype : found_celltypes)
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{
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std::set<std::string> portnames;
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std::set<std::string> parameters;
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std::map<std::string, int> portwidths;
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log("Generate module for cell type %s:\n", celltype.c_str());
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for (auto i1 : design->modules)
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for (auto i2 : i1.second->cells)
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if (i2.second->type == celltype) {
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for (auto &conn : i2.second->connections) {
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if (conn.first[0] != '$')
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portnames.insert(conn.first);
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portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.width);
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}
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for (auto ¶ : i2.second->parameters)
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parameters.insert(para.first);
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}
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for (auto &decl : portdecls)
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if (decl.index > 0)
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portnames.insert(decl.portname);
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std::set<int> indices;
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for (int i = 0; i < int(portnames.size()); i++)
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indices.insert(i+1);
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std::vector<generate_port_decl_t> ports(portnames.size());
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for (auto &decl : portdecls)
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if (decl.index > 0) {
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portwidths[decl.portname] = std::max(portwidths[decl.portname], 1);
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portwidths[decl.portname] = std::max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]);
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log(" port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, RTLIL::id2cstr(decl.portname));
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if (indices.count(decl.index) > ports.size())
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log_error("Port index (%d) exceeds number of found ports (%d).\n", decl.index, int(ports.size()));
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if (indices.count(decl.index) == 0)
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log_error("Conflict on port index %d.\n", decl.index);
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indices.erase(decl.index);
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portnames.erase(decl.portname);
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ports[decl.index-1] = decl;
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}
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while (portnames.size() > 0) {
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std::string portname = *portnames.begin();
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for (auto &decl : portdecls)
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if (decl.index == 0 && !fnmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str(), FNM_NOESCAPE)) {
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generate_port_decl_t d = decl;
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d.portname = portname;
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d.index = *indices.begin();
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assert(!indices.empty());
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indices.erase(d.index);
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ports[d.index-1] = d;
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portwidths[d.portname] = std::max(portwidths[d.portname], 1);
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log(" port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, RTLIL::id2cstr(d.portname));
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goto found_matching_decl;
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}
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log_error("Can't match port %s.\n", RTLIL::id2cstr(portname));
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found_matching_decl:;
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portnames.erase(portname);
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}
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assert(indices.empty());
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RTLIL::Module *mod = new RTLIL::Module;
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mod->name = celltype;
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mod->attributes["\\blackbox"] = RTLIL::Const(1);
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design->modules[mod->name] = mod;
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for (auto &decl : ports) {
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RTLIL::Wire *wire = new RTLIL::Wire;
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wire->name = decl.portname;
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wire->width = portwidths.at(decl.portname);
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wire->port_id = decl.index;
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wire->port_input = decl.input;
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wire->port_output = decl.output;
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mod->add(wire);
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}
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for (auto ¶ : parameters)
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log(" ignoring parameter %s.\n", RTLIL::id2cstr(para));
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log(" module %s created.\n", RTLIL::id2cstr(mod->name));
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}
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}
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static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check)
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{
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bool did_something = false;
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for (auto &cell_it : module->cells) {
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RTLIL::Cell *cell = cell_it.second;
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if (design->modules.count(cell->type) == 0) {
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if (flag_check && cell->type[0] != '$')
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log_error("Module `%s' referenced in module `%s' in cell `%s' is not part of the design.\n",
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cell->type.c_str(), module->name.c_str(), cell->name.c_str());
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continue;
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}
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if (cell->parameters.size() == 0)
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continue;
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if (design->modules.at(cell->type)->get_bool_attribute("\\blackbox"))
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continue;
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RTLIL::Module *mod = design->modules[cell->type];
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cell->type = mod->derive(design, cell->parameters);
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cell->parameters.clear();
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did_something = true;
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}
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return did_something;
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}
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static void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &used, RTLIL::Module *mod, int indent)
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{
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if (used.count(mod) > 0)
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return;
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if (indent == 0)
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log("Top module: %s\n", mod->name.c_str());
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else
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log("Used module: %*s%s\n", indent, "", mod->name.c_str());
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used.insert(mod);
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for (auto &it : mod->cells) {
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if (design->modules.count(it.second->type) > 0)
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hierarchy_worker(design, used, design->modules[it.second->type], indent+4);
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}
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}
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static void hierarchy(RTLIL::Design *design, RTLIL::Module *top)
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{
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std::set<RTLIL::Module*> used;
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hierarchy_worker(design, used, top, 0);
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std::vector<RTLIL::Module*> del_modules;
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for (auto &it : design->modules)
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if (used.count(it.second) == 0)
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del_modules.push_back(it.second);
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for (auto mod : del_modules) {
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log("Removing unused module `%s'.\n", mod->name.c_str());
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design->modules.erase(mod->name);
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delete mod;
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}
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log("Removed %zd unused modules.\n", del_modules.size());
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}
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struct HierarchyPass : public Pass {
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HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" hierarchy [-check] [-top <module>]\n");
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log(" hierarchy -generate <cell-types> <port-decls>\n");
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log("\n");
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log("In parametric designs, a module might exists in serveral variations with\n");
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log("different parameter values. This pass looks at all modules in the current\n");
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log("design an re-runs the language frontends for the parametric modules as\n");
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log("needed.\n");
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log("\n");
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log(" -check\n");
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log(" also check the design hierarchy. this generates an error when\n");
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log(" an unknown module is used as cell type.\n");
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log("\n");
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log(" -keep_positionals\n");
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log(" per default this pass also converts positional arguments in cells\n");
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log(" to arguments using port names. this option disables this behavior.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified top module to built a design hierarchy. modules\n");
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log(" outside this tree (unused modules) are removed.\n");
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log("\n");
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log(" when the -top option is used, the 'top' attribute will be set on the\n");
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log(" specified top module. otherwise a module with the 'top' attribute set\n");
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log(" will implicitly be used as top module, if such a module exists.\n");
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log("\n");
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log("In -generate mode this pass generates blackbox modules for the given cell\n");
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log("types (wildcards supported). For this the design is searched for cells that\n");
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log("match the given types and then the given port declarations are used to\n");
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log("determine the direction of the ports. The syntax for a port declaration is:\n");
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log("\n");
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log(" {i|o|io}[@<num>]:<portname>\n");
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log("\n");
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log("Input ports are specified with the 'i' prefix, output ports with the 'o'\n");
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log("prefix and inout ports with the 'io' prefix. The optional <num> specifies\n");
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log("the position of the port in the parameter list (needed when instanciated\n");
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log("using positional arguments). When <num> is not specified, the <portname> can\n");
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log("also contain wildcard characters.\n");
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log("\n");
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log("This pass ignores the current selection and always operates on all modules\n");
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log("in the current design.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing HIERARCHY pass (managing design hierarchy).\n");
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bool flag_check = false;
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RTLIL::Module *top_mod = NULL;
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bool generate_mode = false;
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bool keep_positionals = false;
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std::vector<std::string> generate_cells;
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std::vector<generate_port_decl_t> generate_ports;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-generate" && !flag_check && !top_mod) {
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generate_mode = true;
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log("Entering generate mode.\n");
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while (++argidx < args.size()) {
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const char *p = args[argidx].c_str();
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generate_port_decl_t decl;
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if (p[0] == 'i' && p[1] == 'o')
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decl.input = true, decl.output = true, p += 2;
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else if (*p == 'i')
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decl.input = true, decl.output = false, p++;
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else if (*p == 'o')
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decl.input = false, decl.output = true, p++;
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else
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goto is_celltype;
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if (*p == '@') {
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char *endptr;
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decl.index = strtol(++p, &endptr, 10);
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if (decl.index < 1)
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goto is_celltype;
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p = endptr;
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} else
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decl.index = 0;
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if (*(p++) != ':')
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goto is_celltype;
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if (*p == 0)
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goto is_celltype;
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decl.portname = p;
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log("Port declaration: %s", decl.input ? decl.output ? "inout" : "input" : "output");
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if (decl.index >= 1)
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log(" [at position %d]", decl.index);
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log(" %s\n", decl.portname.c_str());
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generate_ports.push_back(decl);
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continue;
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is_celltype:
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log("Celltype: %s\n", args[argidx].c_str());
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generate_cells.push_back(RTLIL::unescape_id(args[argidx]));
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}
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continue;
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}
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if (args[argidx] == "-check") {
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flag_check = true;
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continue;
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}
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if (args[argidx] == "-keep_positionals") {
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keep_positionals = true;
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continue;
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}
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if (args[argidx] == "-top") {
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if (++argidx >= args.size())
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log_cmd_error("Option -top requires an additional argument!\n");
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if (args[argidx][0] != '$' && args[argidx][0] != '\\')
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top_mod = design->modules.count("\\" + args[argidx]) > 0 ? design->modules["\\" + args[argidx]] : NULL;
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else
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top_mod = design->modules.count(args[argidx]) > 0 ? design->modules[args[argidx]] : NULL;
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if (top_mod == NULL)
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log_cmd_error("Module `%s' not found!\n", args[argidx].c_str());
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continue;
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}
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break;
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}
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extra_args(args, argidx, design, false);
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if (generate_mode) {
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generate(design, generate_cells, generate_ports);
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return;
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}
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log_push();
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if (top_mod == NULL)
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for (auto &mod_it : design->modules)
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if (mod_it.second->get_bool_attribute("\\top"))
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top_mod = mod_it.second;
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if (top_mod != NULL)
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hierarchy(design, top_mod);
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bool did_something = true;
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bool did_something_once = false;
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while (did_something) {
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did_something = false;
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std::vector<std::string> modnames;
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modnames.reserve(design->modules.size());
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for (auto &mod_it : design->modules)
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modnames.push_back(mod_it.first);
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for (auto &modname : modnames) {
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if (design->modules.count(modname) == 0)
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continue;
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if (expand_module(design, design->modules[modname], flag_check))
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did_something = true;
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}
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if (did_something)
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did_something_once = true;
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}
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if (top_mod != NULL && did_something_once) {
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log_header("Re-running hierarchy analysis..\n");
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hierarchy(design, top_mod);
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}
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if (top_mod != NULL) {
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for (auto &mod_it : design->modules)
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if (mod_it.second == top_mod)
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mod_it.second->attributes["\\top"] = RTLIL::Const(1);
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else
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mod_it.second->attributes.erase("\\top");
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}
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if (!keep_positionals)
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{
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std::set<RTLIL::Module*> pos_mods;
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std::map<std::pair<RTLIL::Module*,int>, RTLIL::IdString> pos_map;
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std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work;
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for (auto &mod_it : design->modules)
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for (auto &cell_it : mod_it.second->cells) {
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RTLIL::Cell *cell = cell_it.second;
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if (design->modules.count(cell->type) == 0)
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continue;
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for (auto &conn : cell->connections)
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if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
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pos_mods.insert(design->modules.at(cell->type));
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pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod_it.second, cell));
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break;
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}
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}
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for (auto module : pos_mods)
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for (auto &wire_it : module->wires) {
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RTLIL::Wire *wire = wire_it.second;
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if (wire->port_id > 0)
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pos_map[std::pair<RTLIL::Module*,int>(module, wire->port_id)] = wire->name;
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}
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for (auto &work : pos_work) {
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RTLIL::Module *module = work.first;
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RTLIL::Cell *cell = work.second;
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log("Mapping positional arguments of cell %s.%s (%s).\n",
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RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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std::map<RTLIL::IdString, RTLIL::SigSpec> new_connections;
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for (auto &conn : cell->connections)
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if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
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int id = atoi(conn.first.c_str()+1);
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std::pair<RTLIL::Module*,int> key(design->modules.at(cell->type), id);
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if (pos_map.count(key) == 0) {
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log(" Failed to map positional argument %d of cell %s.%s (%s).\n",
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id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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new_connections[conn.first] = conn.second;
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} else
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new_connections[pos_map.at(key)] = conn.second;
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} else
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new_connections[conn.first] = conn.second;
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cell->connections = new_connections;
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}
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}
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log_pop();
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}
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} HierarchyPass;
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