mirror of https://github.com/YosysHQ/yosys.git
259 lines
7.2 KiB
C++
259 lines
7.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef MACC_H
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#define MACC_H
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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struct Macc
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{
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struct port_t {
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RTLIL::SigSpec in_a, in_b;
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bool is_signed, do_subtract;
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};
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std::vector<port_t> ports;
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void optimize(int width)
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{
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std::vector<port_t> new_ports;
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RTLIL::Const off(0, width);
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for (auto &port : ports)
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{
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if (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0)
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continue;
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if (GetSize(port.in_a) < GetSize(port.in_b))
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std::swap(port.in_a, port.in_b);
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if (port.in_a.is_fully_const() && port.in_b.is_fully_const()) {
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RTLIL::Const v = port.in_a.as_const();
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if (GetSize(port.in_b))
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v = const_mul(v, port.in_b.as_const(), port.is_signed, port.is_signed, width);
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if (port.do_subtract)
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off = const_sub(off, v, port.is_signed, port.is_signed, width);
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else
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off = const_add(off, v, port.is_signed, port.is_signed, width);
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continue;
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}
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if (port.is_signed) {
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while (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == port.in_a[GetSize(port.in_a)-2])
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port.in_a.remove(GetSize(port.in_a)-1);
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while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])
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port.in_b.remove(GetSize(port.in_b)-1);
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} else {
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while (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == State::S0)
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port.in_a.remove(GetSize(port.in_a)-1);
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while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == State::S0)
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port.in_b.remove(GetSize(port.in_b)-1);
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}
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new_ports.push_back(port);
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}
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if (off.as_bool()) {
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port_t port;
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port.in_a = off;
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port.is_signed = false;
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port.do_subtract = false;
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new_ports.push_back(port);
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}
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new_ports.swap(ports);
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}
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void from_cell_v1(RTLIL::Cell *cell)
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{
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RTLIL::SigSpec port_a = cell->getPort(ID::A);
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ports.clear();
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auto config_bits = cell->getParam(ID::CONFIG);
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int config_cursor = 0;
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int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();
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log_assert(GetSize(config_bits) >= config_width);
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int num_bits = 0;
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if (config_bits[config_cursor++] == State::S1) num_bits |= 1;
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if (config_bits[config_cursor++] == State::S1) num_bits |= 2;
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if (config_bits[config_cursor++] == State::S1) num_bits |= 4;
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if (config_bits[config_cursor++] == State::S1) num_bits |= 8;
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int port_a_cursor = 0;
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while (port_a_cursor < GetSize(port_a))
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{
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log_assert(config_cursor + 2 + 2*num_bits <= config_width);
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port_t this_port;
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this_port.is_signed = config_bits[config_cursor++] == State::S1;
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this_port.do_subtract = config_bits[config_cursor++] == State::S1;
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int size_a = 0;
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for (int i = 0; i < num_bits; i++)
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if (config_bits[config_cursor++] == State::S1)
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size_a |= 1 << i;
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this_port.in_a = port_a.extract(port_a_cursor, size_a);
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port_a_cursor += size_a;
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int size_b = 0;
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for (int i = 0; i < num_bits; i++)
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if (config_bits[config_cursor++] == State::S1)
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size_b |= 1 << i;
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this_port.in_b = port_a.extract(port_a_cursor, size_b);
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port_a_cursor += size_b;
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if (size_a || size_b)
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ports.push_back(this_port);
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}
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for (auto bit : cell->getPort(ID::B))
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ports.push_back(port_t{{bit}, {}, false, false});
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log_assert(config_cursor == config_width);
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log_assert(port_a_cursor == GetSize(port_a));
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}
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void from_cell(RTLIL::Cell *cell)
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{
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if (cell->type == ID($macc)) {
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from_cell_v1(cell);
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return;
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}
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log_assert(cell->type == ID($macc_v2));
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RTLIL::SigSpec port_a = cell->getPort(ID::A);
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RTLIL::SigSpec port_b = cell->getPort(ID::B);
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ports.clear();
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int nterms = cell->getParam(ID::NTERMS).as_int();
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const Const &neg = cell->getParam(ID::TERM_NEGATED);
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const Const &a_widths = cell->getParam(ID::A_WIDTHS);
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const Const &b_widths = cell->getParam(ID::B_WIDTHS);
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const Const &a_signed = cell->getParam(ID::A_SIGNED);
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const Const &b_signed = cell->getParam(ID::B_SIGNED);
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int ai = 0, bi = 0;
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for (int i = 0; i < nterms; i++) {
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port_t term;
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log_assert(a_signed[i] == b_signed[i]);
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term.is_signed = (a_signed[i] == State::S1);
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int a_width = a_widths.extract(16 * i, 16).as_int(false);
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int b_width = b_widths.extract(16 * i, 16).as_int(false);
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term.in_a = port_a.extract(ai, a_width);
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ai += a_width;
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term.in_b = port_b.extract(bi, b_width);
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bi += b_width;
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term.do_subtract = (neg[i] == State::S1);
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ports.push_back(term);
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}
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log_assert(port_a.size() == ai);
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log_assert(port_b.size() == bi);
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}
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void to_cell(RTLIL::Cell *cell)
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{
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cell->type = ID($macc_v2);
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int nterms = ports.size();
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const auto Sx = State::Sx;
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Const a_signed(Sx, nterms), b_signed(Sx, nterms), negated(Sx, nterms);
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Const a_widths, b_widths;
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SigSpec a, b;
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for (int i = 0; i < nterms; i++) {
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SigSpec term_a = ports[i].in_a, term_b = ports[i].in_b;
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a_widths.append(Const(term_a.size(), 16));
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b_widths.append(Const(term_b.size(), 16));
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a_signed.bits()[i] = b_signed.bits()[i] =
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(ports[i].is_signed ? RTLIL::S1 : RTLIL::S0);
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negated.bits()[i] = (ports[i].do_subtract ? RTLIL::S1 : RTLIL::S0);
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a.append(term_a);
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b.append(term_b);
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}
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negated.is_fully_def();
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a_signed.is_fully_def();
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b_signed.is_fully_def();
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cell->setParam(ID::NTERMS, nterms);
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cell->setParam(ID::TERM_NEGATED, negated);
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cell->setParam(ID::A_SIGNED, a_signed);
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cell->setParam(ID::B_SIGNED, b_signed);
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cell->setParam(ID::A_WIDTHS, a_widths);
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cell->setParam(ID::B_WIDTHS, b_widths);
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cell->setPort(ID::A, a);
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cell->setPort(ID::B, b);
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}
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bool eval(RTLIL::Const &result) const
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{
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for (auto &bit : result.bits())
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bit = State::S0;
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for (auto &port : ports)
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{
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if (!port.in_a.is_fully_const() || !port.in_b.is_fully_const())
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return false;
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RTLIL::Const summand;
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if (GetSize(port.in_b) == 0)
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summand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));
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else
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summand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));
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if (port.do_subtract)
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result = const_sub(result, summand, port.is_signed, port.is_signed, GetSize(result));
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else
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result = const_add(result, summand, port.is_signed, port.is_signed, GetSize(result));
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}
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return true;
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}
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bool is_simple_product()
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{
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return ports.size() == 1 &&
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!ports[0].in_b.empty() &&
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!ports[0].do_subtract;
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}
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Macc(RTLIL::Cell *cell = nullptr)
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{
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if (cell != nullptr)
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from_cell(cell);
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}
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};
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YOSYS_NAMESPACE_END
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#endif
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