mirror of https://github.com/YosysHQ/yosys.git
409 lines
13 KiB
C++
409 lines
13 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <assert.h>
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#include <stdio.h>
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#include <string.h>
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#include "passes/techmap/stdcells.inc"
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static void apply_prefix(std::string prefix, std::string &id)
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{
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if (id[0] == '\\')
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id = prefix + "." + id.substr(1);
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else
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id = "$techmap" + prefix + "." + id;
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}
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static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
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{
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for (size_t i = 0; i < sig.chunks.size(); i++) {
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if (sig.chunks[i].wire == NULL)
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continue;
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std::string wire_name = sig.chunks[i].wire->name;
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apply_prefix(prefix, wire_name);
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assert(module->wires.count(wire_name) > 0);
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sig.chunks[i].wire = module->wires[wire_name];
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}
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}
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std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
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std::map<RTLIL::Module*, bool> techmap_fail_cache;
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std::set<RTLIL::Module*> techmap_opt_cache;
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static bool techmap_fail_check(RTLIL::Module *module)
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{
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if (module == NULL)
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return false;
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if (techmap_fail_cache.count(module) > 0)
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return techmap_fail_cache.at(module);
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for (auto &it : module->wires) {
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std::string name = it.first;
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if (name == "\\TECHMAP_FAIL")
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return techmap_fail_cache[module] = true;
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if (name.size() > 13 && name[0] == '\\' && name.substr(name.size()-13) == ".TECHMAP_FAIL")
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return techmap_fail_cache[module] = true;
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}
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return techmap_fail_cache[module] = false;
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}
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static void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, RTLIL::Selection &new_members, bool flatten_mode)
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{
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log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name));
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if (tpl->memories.size() != 0)
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log_error("Technology map yielded memories -> this is not supported.\n");
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if (tpl->processes.size() != 0)
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log_error("Technology map yielded processes -> this is not supported.\n");
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std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
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for (auto &it : tpl->wires) {
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if (it.second->port_id > 0)
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positional_ports[stringf("$%d", it.second->port_id)] = it.first;
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RTLIL::Wire *w = new RTLIL::Wire(*it.second);
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apply_prefix(cell->name, w->name);
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w->port_input = false;
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w->port_output = false;
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w->port_id = 0;
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module->wires[w->name] = w;
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design->select(module, w);
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new_members.select(module, w);
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}
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SigMap port_signal_map;
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for (auto &it : cell->connections) {
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RTLIL::IdString portname = it.first;
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if (positional_ports.count(portname) > 0)
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portname = positional_ports.at(portname);
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if (tpl->wires.count(portname) == 0 || tpl->wires.at(portname)->port_id == 0) {
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if (portname.substr(0, 1) == "$")
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log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
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continue;
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}
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RTLIL::Wire *w = tpl->wires.at(portname);
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RTLIL::SigSig c;
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if (w->port_output) {
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c.first = it.second;
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c.second = RTLIL::SigSpec(w);
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apply_prefix(cell->name, c.second, module);
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} else {
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c.first = RTLIL::SigSpec(w);
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c.second = it.second;
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apply_prefix(cell->name, c.first, module);
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}
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if (c.second.width > c.first.width)
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c.second.remove(c.first.width, c.second.width - c.first.width);
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if (c.second.width < c.first.width)
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c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width));
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assert(c.first.width == c.second.width);
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#if 0
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// more conservative approach:
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// connect internal and external wires
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module->connections.push_back(c);
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#else
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// approach that yields nicer outputs:
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// replace internal wires that are connected to external wires
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if (w->port_output)
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port_signal_map.add(c.second, c.first);
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else
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port_signal_map.add(c.first, c.second);
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#endif
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}
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for (auto &it : tpl->cells) {
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RTLIL::Cell *c = new RTLIL::Cell(*it.second);
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if (!flatten_mode && c->type.substr(0, 2) == "\\$")
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c->type = c->type.substr(1);
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apply_prefix(cell->name, c->name);
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for (auto &it2 : c->connections) {
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apply_prefix(cell->name, it2.second, module);
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port_signal_map.apply(it2.second);
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}
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module->cells[c->name] = c;
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design->select(module, c);
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new_members.select(module, c);
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}
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for (auto &it : tpl->connections) {
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RTLIL::SigSig c = it;
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apply_prefix(cell->name, c.first, module);
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apply_prefix(cell->name, c.second, module);
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port_signal_map.apply(c.first);
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port_signal_map.apply(c.second);
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module->connections.push_back(c);
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}
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module->cells.erase(cell->name);
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delete cell;
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}
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static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
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const std::map<RTLIL::IdString, std::set<RTLIL::IdString>> &celltypeMap, bool flatten_mode, bool opt_mode)
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{
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if (!design->selected(module))
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return false;
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bool did_something = false;
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std::vector<std::string> cell_names;
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RTLIL::Selection new_members(false);
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for (auto &cell_it : module->cells)
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cell_names.push_back(cell_it.first);
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for (auto &cell_name : cell_names)
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{
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if (module->cells.count(cell_name) == 0)
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continue;
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RTLIL::Cell *cell = module->cells[cell_name];
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if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
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continue;
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if (celltypeMap.count(cell->type) == 0)
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continue;
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for (auto &tpl_name : celltypeMap.at(cell->type))
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{
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std::string derived_name = tpl_name;
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RTLIL::Module *tpl = map->modules[tpl_name];
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std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
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for (auto conn : cell->connections) {
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if (conn.first.substr(0, 1) == "$")
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continue;
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if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0)
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continue;
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if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0)
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goto next_tpl;
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parameters[conn.first] = conn.second.as_const();
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}
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if (0) {
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next_tpl:
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continue;
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}
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bool log_continue = false;
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std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
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if (techmap_cache.count(key) > 0) {
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tpl = techmap_cache[key];
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} else {
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if (cell->parameters.size() != 0) {
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derived_name = tpl->derive(map, parameters);
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tpl = map->modules[derived_name];
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log_continue = true;
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}
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techmap_cache[key] = tpl;
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}
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if (techmap_fail_check(tpl)) {
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if (log_continue)
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log_header("Continuing TECHMAP pass.\n");
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log("Not using module `%s' from techmap as it contains a TECHMAP_FAIL marker wire.\n", derived_name.c_str());
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continue;
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}
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if (opt_mode && techmap_opt_cache.count(tpl) == 0) {
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Pass::call(map, "opt " + tpl->name);
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techmap_opt_cache.insert(tpl);
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log_continue = true;
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}
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if (log_continue)
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log_header("Continuing TECHMAP pass.\n");
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techmap_module_worker(design, module, cell, tpl, new_members, flatten_mode);
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did_something = true;
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cell = NULL;
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break;
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}
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handled_cells.insert(cell);
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}
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if (did_something && opt_mode) {
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design->selection_stack.push_back(new_members);
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Pass::call(design, "opt_const");
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log_header("Continuing TECHMAP pass.\n");
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design->selection_stack.pop_back();
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}
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return did_something;
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}
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struct TechmapPass : public Pass {
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TechmapPass() : Pass("techmap", "simple technology mapper") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" techmap [-map filename] [selection]\n");
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log("\n");
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log("This pass implements a very simple technology mapper that replaces cells in\n");
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log("the design with implementations given in form of a verilog or ilang source\n");
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log("file.\n");
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log("\n");
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log(" -map filename\n");
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log(" the library of cell implementations to be used.\n");
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log(" without this parameter a builtin library is used that\n");
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log(" transforms the internal RTL cells to the internal gate\n");
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log(" library.\n");
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log("\n");
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log(" -opt\n");
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log(" run 'opt' pass on all cells from map file before using them and run\n");
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log(" 'opt_const' on all replacement cells before mapping recursively.\n");
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log("\n");
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log("When a module in the map file has the 'celltype' attribute set, it will match\n");
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log("cells with a type that match the text value of this attribute.\n");
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log("\n");
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log("When a module in the map file contains a wire with the name 'TECHMAP_FAIL' (or\n");
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log("one matching '*.TECHMAP_FAIL') then no substitution will be performed. The\n");
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log("modules in the map file are tried in alphabetical order.\n");
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log("\n");
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log("When a module in the map file has a parameter where the according cell in the\n");
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log("design has a port, the module from the map file is only used if the port in\n");
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log("the design is connected to a constant value. The parameter is then set to the\n");
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log("constant value.\n");
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log("\n");
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log("See 'help extract' for a pass that does the opposite thing.\n");
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log("\n");
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log("See 'help flatten' for a pass that does flatten the design (which is\n");
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log("esentially techmap but using the design itself as map library).\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing TECHMAP pass (map to technology primitives).\n");
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log_push();
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std::string filename;
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bool opt_mode = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-map" && argidx+1 < args.size()) {
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filename = args[++argidx];
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continue;
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}
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if (args[argidx] == "-opt") {
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opt_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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FILE *f = filename.empty() ? fmemopen(stdcells_code, strlen(stdcells_code), "rt") : fopen(filename.c_str(), "rt");
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if (f == NULL)
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log_cmd_error("Can't open map file `%s'\n", filename.c_str());
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RTLIL::Design *map = new RTLIL::Design;
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Frontend::frontend_call(map, f, filename.empty() ? "<stdcells.v>" : filename,
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(filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
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fclose(f);
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std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
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for (auto &it : map->modules) {
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if (it.first.substr(0, 2) == "\\$")
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it.second->name = it.first.substr(1);
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modules_new[it.second->name] = it.second;
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}
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map->modules.swap(modules_new);
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std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
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for (auto &it : map->modules) {
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if (it.second->attributes.count("\\celltype") && !it.second->attributes.at("\\celltype").str.empty()) {
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celltypeMap[RTLIL::escape_id(it.second->attributes.at("\\celltype").str)].insert(it.first);
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} else
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celltypeMap[it.first].insert(it.first);
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}
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bool did_something = true;
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std::set<RTLIL::Cell*> handled_cells;
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while (did_something) {
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did_something = false;
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for (auto &mod_it : design->modules)
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if (techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false, opt_mode))
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did_something = true;
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if (did_something)
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design->check();
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}
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log("No more expansions possible.\n");
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techmap_cache.clear();
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techmap_fail_cache.clear();
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techmap_opt_cache.clear();
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delete map;
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log_pop();
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}
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} TechmapPass;
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struct FlattenPass : public Pass {
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FlattenPass() : Pass("flatten", "flatten design") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" flatten [selection]\n");
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log("\n");
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log("This pass flattens the design by replacing cells by their implementation. This\n");
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log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
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log("pass is using the current design as mapping library.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing FLATTEN pass (flatten design).\n");
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log_push();
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extra_args(args, 1, design);
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std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
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for (auto &it : design->modules)
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celltypeMap[it.first].insert(it.first);
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bool did_something = true;
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std::set<RTLIL::Cell*> handled_cells;
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while (did_something) {
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did_something = false;
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for (auto &mod_it : design->modules)
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if (techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true, false))
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did_something = true;
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}
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log("No more expansions possible.\n");
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techmap_cache.clear();
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techmap_fail_cache.clear();
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techmap_opt_cache.clear();
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log_pop();
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}
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} FlattenPass;
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