Clifford Wolf 752553d8e9 Merge pull request #946 from YosysHQ/clifford/specify ... Add specify parser		2019-05-06 20:57:15 +02:00
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.gitignore	Add "make coverage"	2018-08-27 14:22:21 +02:00
Makefile.inc	Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906	2019-03-29 16:32:44 +01:00
const2ast.cc	Convert more log_error() to log_file_error() where possible.	2018-07-20 09:37:44 -07:00
preproc.cc	Support SystemVerilog `` extension for macros	2018-05-17 00:09:56 -04:00
verilog_frontend.cc	Merge remote-tracking branch 'origin/master' into clifford/specify	2019-05-03 15:05:57 -07:00
verilog_frontend.h	Add specify parser	2019-04-23 21:36:59 +02:00
verilog_lexer.l	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify	2019-05-06 11:46:10 +02:00
verilog_parser.y	Merge pull request #946 from YosysHQ/clifford/specify	2019-05-06 20:57:15 +02:00