yosys/techlibs
Andrew Zonenberg c53a33143e greenpak4: Can now techmap inferred D latches (without set/reset or output inverter) 2016-12-10 18:46:36 +08:00
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common Added $anyseq cell type 2016-10-14 15:24:03 +02:00
gowin Indenting fixes in gowin sim cell lib 2016-11-08 18:54:00 +01:00
greenpak4 greenpak4: Can now techmap inferred D latches (without set/reset or output inverter) 2016-12-10 18:46:36 +08:00
ice40 iCE40 flow is not experimental anymore 2016-11-01 11:32:02 +01:00
xilinx Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00