mirror of https://github.com/YosysHQ/yosys.git
c50afc4246
- Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport) |
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| cmds | ||
| equiv | ||
| fsm | ||
| hierarchy | ||
| memory | ||
| opt | ||
| proc | ||
| sat | ||
| techmap | ||
| tests | ||