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yosys/frontends/ast
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Ruben Undheim c50afc4246 Documentation improvements etc. 
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
 		2018-10-13 20:34:44 +02:00
..
Makefile.inc Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 12:43:51 +02:00
ast.cc Documentation improvements etc. 2018-10-13 20:34:44 +02:00
ast.h Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
dpicall.cc Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
genrtlil.cc Documentation improvements etc. 2018-10-13 20:34:44 +02:00
simplify.cc Synthesis support for SystemVerilog interfaces 2018-10-12 21:11:36 +02:00