yosys/techlibs/anlogic/lutrams.txt

ram distributed $__ANLOGIC_DRAM16X4_ {
	abits 4;
	width 4;
	cost 4;
	init no_undef;
	prune_rom;
	port sw "W" {
		clock posedge;
	}
	port ar "R" {
	}
}