yosys/passes/fsm
Clifford Wolf 788bd02f97 Fixed FSM mapping for multiple reset-like signals 2014-08-10 12:04:02 +02:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
fsm.cc Fixed "fsm -export" 2014-08-08 14:56:03 +02:00
fsm_detect.cc More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
fsm_expand.cc Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
fsm_export.cc Fixed "fsm -export" 2014-08-08 14:56:03 +02:00
fsm_extract.cc Another fsm_extract bugfix 2014-08-08 14:56:04 +02:00
fsm_info.cc Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
fsm_map.cc Fixed FSM mapping for multiple reset-like signals 2014-08-10 12:04:02 +02:00
fsm_opt.cc Some improvements in fsm_opt and fsm_map for FSM with unreachable states 2014-08-09 14:49:51 +02:00
fsm_recode.cc Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
fsmdata.h Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00