mirror of https://github.com/YosysHQ/yosys.git
244 lines
6.5 KiB
C++
244 lines
6.5 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "blifparse.h"
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#include "kernel/log.h"
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#include <stdio.h>
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#include <string.h>
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static bool read_next_line(char *&buffer, size_t &buffer_size, int &line_count, FILE *f)
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{
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int buffer_len = 0;
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buffer[0] = 0;
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while (1)
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{
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buffer_len += strlen(buffer + buffer_len);
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while (buffer_len > 0 && (buffer[buffer_len-1] == ' ' || buffer[buffer_len-1] == '\t' ||
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buffer[buffer_len-1] == '\r' || buffer[buffer_len-1] == '\n'))
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buffer[--buffer_len] = 0;
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if (buffer_size-buffer_len < 4096) {
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buffer_size *= 2;
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buffer = (char*)realloc(buffer, buffer_size);
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}
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if (buffer_len == 0 || buffer[buffer_len-1] == '\\') {
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if (buffer_len > 0 && buffer[buffer_len-1] == '\\')
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buffer[--buffer_len] = 0;
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line_count++;
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if (fgets(buffer+buffer_len, buffer_size-buffer_len, f) == NULL)
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return false;
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} else
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return true;
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}
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}
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RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
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{
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RTLIL::Design *design = new RTLIL::Design;
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RTLIL::Module *module = new RTLIL::Module;
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RTLIL::Const *lutptr = NULL;
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RTLIL::State lut_default_state = RTLIL::State::Sx;
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int port_count = 0;
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module->name = "\\netlist";
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design->add(module);
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size_t buffer_size = 4096;
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char *buffer = (char*)malloc(buffer_size);
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int line_count = 0;
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while (1)
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{
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if (!read_next_line(buffer, buffer_size, line_count, f))
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goto error;
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continue_without_read:
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if (buffer[0] == '#')
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continue;
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if (buffer[0] == '.')
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{
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if (lutptr) {
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for (auto &bit : lutptr->bits)
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if (bit == RTLIL::State::Sx)
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bit = lut_default_state;
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lutptr = NULL;
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lut_default_state = RTLIL::State::Sx;
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}
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char *cmd = strtok(buffer, " \t\r\n");
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if (!strcmp(cmd, ".model"))
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continue;
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if (!strcmp(cmd, ".end")) {
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free(buffer);
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return design;
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}
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if (!strcmp(cmd, ".inputs") || !strcmp(cmd, ".outputs")) {
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char *p;
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while ((p = strtok(NULL, " \t\r\n")) != NULL) {
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RTLIL::Wire *wire = module->addWire(stringf("\\%s", p));
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wire->port_id = ++port_count;
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if (!strcmp(cmd, ".inputs"))
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wire->port_input = true;
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else
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wire->port_output = true;
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}
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continue;
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}
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if (!strcmp(cmd, ".latch"))
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{
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char *d = strtok(NULL, " \t\r\n");
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char *q = strtok(NULL, " \t\r\n");
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if (module->wires_.count(RTLIL::escape_id(d)) == 0)
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module->addWire(RTLIL::escape_id(d));
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if (module->wires_.count(RTLIL::escape_id(q)) == 0)
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module->addWire(RTLIL::escape_id(q));
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RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name);
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cell->setPort("\\D", module->wires_.at(RTLIL::escape_id(d)));
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cell->setPort("\\Q", module->wires_.at(RTLIL::escape_id(q)));
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continue;
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}
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if (!strcmp(cmd, ".gate"))
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{
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char *p = strtok(NULL, " \t\r\n");
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if (p == NULL)
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goto error;
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RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(p));
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while ((p = strtok(NULL, " \t\r\n")) != NULL) {
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char *q = strchr(p, '=');
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if (q == NULL || !q[0] || !q[1])
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goto error;
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*(q++) = 0;
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if (module->wires_.count(RTLIL::escape_id(q)) == 0)
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module->addWire(RTLIL::escape_id(q));
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cell->setPort(RTLIL::escape_id(p), module->wires_.at(RTLIL::escape_id(q)));
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}
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continue;
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}
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if (!strcmp(cmd, ".names"))
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{
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char *p;
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RTLIL::SigSpec input_sig, output_sig;
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while ((p = strtok(NULL, " \t\r\n")) != NULL) {
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RTLIL::Wire *wire;
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if (module->wires_.count(stringf("\\%s", p)) > 0) {
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wire = module->wires_.at(stringf("\\%s", p));
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} else {
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wire = module->addWire(stringf("\\%s", p));
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}
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input_sig.append(wire);
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}
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output_sig = input_sig.extract(input_sig.size()-1, 1);
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input_sig = input_sig.extract(0, input_sig.size()-1);
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if (input_sig.size() == 0) {
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RTLIL::State state = RTLIL::State::Sa;
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while (1) {
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if (!read_next_line(buffer, buffer_size, line_count, f))
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goto error;
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for (int i = 0; buffer[i]; i++) {
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if (buffer[i] == ' ' || buffer[i] == '\t')
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continue;
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if (i == 0 && buffer[i] == '.')
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goto finished_parsing_constval;
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if (buffer[i] == '0') {
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if (state == RTLIL::State::S1)
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goto error;
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state = RTLIL::State::S0;
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continue;
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}
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if (buffer[i] == '1') {
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if (state == RTLIL::State::S0)
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goto error;
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state = RTLIL::State::S1;
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continue;
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}
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goto error;
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}
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}
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finished_parsing_constval:
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if (state == RTLIL::State::Sa)
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state = RTLIL::State::S1;
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module->connect(RTLIL::SigSig(output_sig, state));
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goto continue_without_read;
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}
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RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
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cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
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cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
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cell->setPort("\\I", input_sig);
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cell->setPort("\\O", output_sig);
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lutptr = &cell->parameters.at("\\LUT");
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lut_default_state = RTLIL::State::Sx;
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continue;
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}
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goto error;
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}
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if (lutptr == NULL)
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goto error;
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char *input = strtok(buffer, " \t\r\n");
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char *output = strtok(NULL, " \t\r\n");
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if (input == NULL || output == NULL || (strcmp(output, "0") && strcmp(output, "1")))
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goto error;
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int input_len = strlen(input);
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if (input_len > 8)
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goto error;
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for (int i = 0; i < (1 << input_len); i++) {
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for (int j = 0; j < input_len; j++) {
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char c1 = input[j];
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if (c1 != '-') {
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char c2 = (i & (1 << j)) != 0 ? '1' : '0';
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if (c1 != c2)
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goto try_next_value;
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}
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}
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lutptr->bits.at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1;
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try_next_value:;
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}
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lut_default_state = !strcmp(output, "0") ? RTLIL::State::S1 : RTLIL::State::S0;
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}
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error:
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log_error("Syntax error in line %d!\n", line_count);
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// delete design;
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// return NULL;
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}
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