mirror of https://github.com/YosysHQ/yosys.git
41 lines
1.0 KiB
Verilog
41 lines
1.0 KiB
Verilog
module top(...);
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input [3:0] a;
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output o1_1 = 4'b0000 > a;
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output o1_2 = 4'b0000 <= a;
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output o1_3 = 4'b1111 < a;
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output o1_4 = 4'b1111 >= a;
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output o1_5 = a < 4'b0000;
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output o1_6 = a >= 4'b0000;
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output o1_7 = a > 4'b1111;
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output o1_8 = a <= 4'b1111;
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output o2_1 = 4'sb0000 > $signed(a);
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output o2_2 = 4'sb0000 <= $signed(a);
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output o2_3 = $signed(a) < 4'sb0000;
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output o2_4 = $signed(a) >= 4'sb0000;
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output o3_1 = 4'b0100 > a;
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output o3_2 = 4'b0100 <= a;
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output o3_3 = a < 4'b0100;
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output o3_4 = a >= 4'b0100;
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output o4_1 = 5'b10000 > a;
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output o4_2 = 5'b10000 >= a;
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output o4_3 = 5'b10000 < a;
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output o4_4 = 5'b10000 <= a;
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output o4_5 = a < 5'b10000;
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output o4_6 = a <= 5'b10000;
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output o4_7 = a > 5'b10000;
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output o4_8 = a >= 5'b10000;
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output o5_1 = 5'b10100 > a;
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output o5_2 = 5'b10100 >= a;
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output o5_3 = 5'b10100 < a;
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output o5_4 = 5'b10100 <= a;
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output o5_5 = a < 5'b10100;
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output o5_6 = a <= 5'b10100;
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output o5_7 = a > 5'b10100;
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output o5_8 = a >= 5'b10100;
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endmodule
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