riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/manual/PRESENTATION_ExSyn/opt_03.v

5 lines
102 B
Verilog
Raw Blame History

module test(input [3:0] A, B,
output [3:0] Y, Z);
assign Y = A + B, Z = B + A;
endmodule
Reference in New Issue View Git Blame Copy Permalink