mirror of https://github.com/YosysHQ/yosys.git
25 lines
451 B
Verilog
25 lines
451 B
Verilog
module test(
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input clk, wen,
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input [4:0] waddr, raddr,
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input [31:0] wdata,
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output reg [31:0] rdata,
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signed input [7:0] a, b, x,
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output [15:0] s, d, y, z, u, q
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);
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reg [31:0] memory [0:31];
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always @(posedge clk) begin
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rdata <= memory[raddr];
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if (wen) memory[waddr] <= wdata;
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end
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assign s = a+{b[6:2], 2'b1};
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assign d = a-b;
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assign y = x;
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assign z[7:0] = s+d;
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assign z[15:8] = s-d;
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always @(posedge clk)
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q <= s ^ d ^ x;
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endmodule
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