yosys/techlibs
Andrew Zonenberg c04a3d2763 Fixed typo (wasn't written in 2012) 2016-03-30 23:58:45 -07:00
..
common Added more cell help messages 2016-03-29 15:14:43 +02:00
greenpak4 Fixed typo (wasn't written in 2012) 2016-03-30 23:58:45 -07:00
ice40 Work around DDR dout sim glitches in ice40 SB_IO sim model 2016-02-07 11:19:48 +01:00
xilinx Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00