mirror of https://github.com/YosysHQ/yosys.git
141 lines
4.0 KiB
Verilog
141 lines
4.0 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// ============================================================================
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module \$__ABC_ASYNC (input A, S, output Y);
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assign Y = A;
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endmodule
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module \$__ABC_FDRE (output Q,
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input C,
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input CE,
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input D,
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input R, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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parameter CLK_POLARITY = !IS_C_INVERTED;
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parameter EN_POLARITY = 1'b1;
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FDRE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_R_INVERTED(IS_R_INVERTED),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
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);
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endmodule
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module \$__ABC_FDRE_1 (output Q,
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input C,
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input CE,
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input D,
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input R, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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parameter CLK_POLARITY = 1'b0;
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parameter EN_POLARITY = 1'b1;
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assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
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FDRE_1 #(
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.INIT(INIT),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
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);
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endmodule
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module \$__ABC_FDCE (output Q,
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input C,
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input CE,
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input D,
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input CLR, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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parameter CLK_POLARITY = !IS_C_INVERTED;
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parameter EN_POLARITY = 1'b1;
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FDCE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_CLR_INVERTED(IS_CLR_INVERTED),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
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);
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endmodule
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module \$__ABC_FDCE_1 (output Q,
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input C,
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input CE,
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input D,
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input CLR, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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parameter CLK_POLARITY = 1'b0;
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parameter EN_POLARITY = 1'b1;
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FDCE_1 #(
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.INIT(INIT),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
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);
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endmodule
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module \$__ABC_FDPE (output Q,
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input C,
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input CE,
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input D,
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input PRE, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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parameter CLK_POLARITY = !IS_C_INVERTED;
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parameter EN_POLARITY = 1'b1;
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FDPE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_PRE_INVERTED(IS_PRE_INVERTED),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
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);
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endmodule
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module \$__ABC_FDPE_1 (output Q,
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input C,
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input CE,
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input D,
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input PRE, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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parameter CLK_POLARITY = 1'b0;
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parameter EN_POLARITY = 1'b1;
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FDPE_1 #(
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.INIT(INIT),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
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);
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endmodule
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