mirror of https://github.com/YosysHQ/yosys.git
37 lines
499 B
Verilog
37 lines
499 B
Verilog
module \$_MUX8_ (
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A, B, C, D, E, F, G, H, S, T, U, Y
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);
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input A, B, C, D, E, F, G, H, S, T, U;
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output Y;
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mux8x0 _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.C(C),
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.D(D),
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.E(E),
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.F(F),
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.G(G),
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.H(H),
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.S0(S),
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.S1(T),
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.S2(U),
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.Q(Y)
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);
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endmodule
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module \$_MUX4_ (
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A, B, C, D, S, T, U, Y
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);
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input A, B, C, D, S, T, U;
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output Y;
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mux4x0 _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.C(C),
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.D(D),
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.S0(S),
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.S1(T),
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.Q(Y)
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);
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endmodule
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