mirror of https://github.com/YosysHQ/yosys.git
266 lines
6.8 KiB
C++
266 lines
6.8 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2022 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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#include "kernel/ffinit.h"
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#include "kernel/ff.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OptFfInvWorker
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{
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int count = 0;
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RTLIL::Module *module;
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ModIndex index;
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FfInitVals initvals;
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// Case 1:
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// - FF is driven by inverter
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// - ... which has no other users
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// - all users of FF are LUTs
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bool push_d_inv(FfData &ff) {
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if (index.query_is_input(ff.sig_d))
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return false;
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if (index.query_is_output(ff.sig_d))
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return false;
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auto d_ports = index.query_ports(ff.sig_d);
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if (d_ports.size() != 2)
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return false;
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Cell *d_inv = nullptr;
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for (auto &port: d_ports) {
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if (port.cell == ff.cell && port.port == ID::D)
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continue;
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if (port.port != ID::Y)
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return false;
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if (port.cell->type.in(ID($not), ID($_NOT_))) {
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// OK
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} else if (port.cell->type.in(ID($lut))) {
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if (port.cell->getParam(ID::WIDTH) != 1)
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return false;
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if (port.cell->getParam(ID::LUT).as_int() != 1)
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return false;
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} else {
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return false;
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}
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log_assert(d_inv == nullptr);
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d_inv = port.cell;
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}
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if (index.query_is_output(ff.sig_q))
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return false;
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auto q_ports = index.query_ports(ff.sig_q);
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pool<Cell *> q_luts;
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for (auto &port: q_ports) {
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if (port.cell == ff.cell && port.port == ID::Q)
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continue;
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if (port.cell == d_inv)
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return false;
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if (port.port != ID::A)
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return false;
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if (!port.cell->type.in(ID($not), ID($_NOT_), ID($lut)))
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return false;
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q_luts.insert(port.cell);
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}
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ff.flip_rst_bits({0});
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ff.sig_d = d_inv->getPort(ID::A);
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for (Cell *lut: q_luts) {
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if (lut->type == ID($lut)) {
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int flip_mask = 0;
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SigSpec sig_a = lut->getPort(ID::A);
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for (int i = 0; i < GetSize(sig_a); i++) {
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if (index.sigmap(sig_a[i]) == index.sigmap(ff.sig_q)) {
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flip_mask |= 1 << i;
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}
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}
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Const mask = lut->getParam(ID::LUT);
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Const new_mask;
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for (int j = 0; j < (1 << GetSize(sig_a)); j++) {
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new_mask.bits.push_back(mask.bits[j ^ flip_mask]);
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}
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if (GetSize(sig_a) == 1 && new_mask.as_int() == 2) {
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module->connect(lut->getPort(ID::Y), ff.sig_q);
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module->remove(lut);
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} else {
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lut->setParam(ID::LUT, new_mask);
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}
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} else {
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// it was an inverter
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module->connect(lut->getPort(ID::Y), ff.sig_q);
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module->remove(lut);
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}
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}
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ff.emit();
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return true;
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}
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// Case 2:
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// - FF is driven by LUT
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// - ... which has no other users
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// - FF has one user
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// - ... which is an inverter
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bool push_q_inv(FfData &ff) {
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if (index.query_is_input(ff.sig_d))
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return false;
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if (index.query_is_output(ff.sig_d))
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return false;
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Cell *d_lut = nullptr;
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auto d_ports = index.query_ports(ff.sig_d);
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if (d_ports.size() != 2)
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return false;
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for (auto &port: d_ports) {
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if (port.cell == ff.cell && port.port == ID::D)
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continue;
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if (port.port != ID::Y)
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return false;
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if (!port.cell->type.in(ID($not), ID($_NOT_), ID($lut)))
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return false;
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log_assert(d_lut == nullptr);
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d_lut = port.cell;
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}
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if (index.query_is_output(ff.sig_q))
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return false;
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auto q_ports = index.query_ports(ff.sig_q);
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if (q_ports.size() != 2)
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return false;
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Cell *q_inv = nullptr;
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for (auto &port: q_ports) {
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if (port.cell == ff.cell && port.port == ID::Q)
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continue;
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if (port.cell == d_lut)
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return false;
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if (port.port != ID::A)
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return false;
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if (port.cell->type.in(ID($not), ID($_NOT_))) {
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// OK
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} else if (port.cell->type.in(ID($lut))) {
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if (port.cell->getParam(ID::WIDTH) != 1)
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return false;
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if (port.cell->getParam(ID::LUT).as_int() != 1)
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return false;
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} else {
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return false;
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}
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log_assert(q_inv == nullptr);
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q_inv = port.cell;
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}
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ff.flip_rst_bits({0});
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ff.sig_q = q_inv->getPort(ID::Y);
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module->remove(q_inv);
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if (d_lut->type == ID($lut)) {
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Const mask = d_lut->getParam(ID::LUT);
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Const new_mask;
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for (int i = 0; i < GetSize(mask); i++) {
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if (mask.bits[i] == State::S0)
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new_mask.bits.push_back(State::S1);
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else
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new_mask.bits.push_back(State::S0);
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}
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d_lut->setParam(ID::LUT, new_mask);
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if (d_lut->getParam(ID::WIDTH) == 1 && new_mask.as_int() == 2) {
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module->connect(ff.sig_d, d_lut->getPort(ID::A));
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module->remove(d_lut);
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}
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} else {
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// it was an inverter
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module->connect(ff.sig_d, d_lut->getPort(ID::A));
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module->remove(d_lut);
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}
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ff.emit();
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return true;
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}
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OptFfInvWorker(RTLIL::Module *module) :
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module(module), index(module), initvals(&index.sigmap, module)
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{
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log("Discovering LUTs.\n");
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std::vector<Cell *> ffs;
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for (Cell *cell : module->selected_cells())
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if (RTLIL::builtin_ff_cell_types().count(cell->type))
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ffs.push_back(cell);
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for (Cell *cell : ffs) {
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FfData ff(&initvals, cell);
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if (ff.has_sr)
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continue;
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if (!ff.has_clk)
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continue;
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if (ff.has_aload)
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continue;
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if (ff.width != 1)
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continue;
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if (push_d_inv(ff)) {
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count++;
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} else if (push_q_inv(ff)) {
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count++;
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}
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}
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}
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};
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struct OptFfInvPass : public Pass {
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OptFfInvPass() : Pass("opt_ffinv", "push inverters through FFs") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_ffinv [selection]\n");
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log("\n");
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log("This pass pushes inverters to the other side of a FF when they can be merged\n");
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log("into LUTs on the other side.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing OPT_FFINV pass (push inverters through FFs).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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break;
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}
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extra_args(args, argidx, design);
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int total_count = 0;
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for (auto module : design->selected_modules())
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{
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OptFfInvWorker worker(module);
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total_count += worker.count;
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}
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if (total_count)
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design->scratchpad_set_bool("opt.did_something", true);
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log("Pushed %d inverters.\n", total_count);
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}
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} OptFfInvPass;
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PRIVATE_NAMESPACE_END
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